[coreboot-gerrit] Change in coreboot[master]: riscv: bug in fetch instruction

[Anonymous Coward (Code Review)]

Anonymous Coward #1001664 has uploaded this change for review. ( https://review.coreboot.org/20105


Change subject: riscv: bug in fetch instruction
......................................................................

riscv: bug in fetch instruction

I encountered a problem when i debug the code. The bug is continuously
trap in misaligned load.This is caused by the fetch in the exception
handling. Direct read 32bit value not care address alignment. But riscv
have 16bit instruction.

Change-Id: I2b96c73f6bbd8e5a6e0ff66944235fc179a29fe9
Signed-off-by: wxjstz <wxjstz at 126.com>
---
M src/arch/riscv/trap_handler.c
1 file changed, 6 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/20105/1

diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index 4dd3d5b..d64a04b 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -233,7 +233,12 @@
 
 static uint32_t fetch_instruction(uintptr_t vaddr) {
 	printk(BIOS_SPEW, "fetching instruction at 0x%016zx\n", (size_t)vaddr);
-	return mprv_read_u32((uint32_t *) vaddr);
+	uint32_t value = 0;
+	for(int i=0;i<2;i++){
+		value <<= 16;
+		value += mprv_read_u16((uint16_t *)vaddr + i);
+	}
+	return value;
 }
 
 void handle_misaligned_load(trapframe *tf) {

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2b96c73f6bbd8e5a6e0ff66944235fc179a29fe9
Gerrit-Change-Number: 20105
Gerrit-PatchSet: 1
Gerrit-Owner: Anonymous Coward #1001664