[coreboot-gerrit] Change in coreboot[master]: src/cpu/amd/atrr/amd_mtrr.c Fix checkpatch errors + warnings

[Evelyn Huang (Code Review)]

Evelyn Huang has uploaded this change for review. ( https://review.coreboot.org/20097


Change subject: src/cpu/amd/atrr/amd_mtrr.c Fix checkpatch errors + warnings
......................................................................

src/cpu/amd/atrr/amd_mtrr.c Fix checkpatch errors + warnings

Fix line over 80 characters, unnecessary braces for single statement
blocks, spaces before close parantheses errors and warnings.

Signed-off-by: Evelyn Huang <evhuang at google.com>

Change-Id: I31b1932a2c1e401e56751e0c790bcc6287fb550d
---
M src/cpu/amd/mtrr/amd_mtrr.c
1 file changed, 10 insertions(+), 8 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/20097/1

diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index 6c0ead2..106cb79 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -103,9 +103,12 @@
 	const int cpu_id = cpuid_eax(0x80000001);
 	printk(BIOS_SPEW, "CPU ID 0x80000001: %x\n", cpu_id);
 	const int has_tom2wb =
-		 (((cpu_id>>20 )&0xf) > 0) || // ExtendedFamily > 0
-		((((cpu_id>>8 )&0xf) == 0xf) && // Family == 0F
-		 (((cpu_id>>16)&0xf) >= 0x4));  // Rev>=F deduced from rev tables
+		// ExtendedFamily > 0
+		 (((cpu_id>>20)&0xf) > 0) ||
+		// Family == 0F
+		((((cpu_id>>8)&0xf) == 0xf) &&
+		// Rev>=F deduced from rev tables
+		 (((cpu_id>>16)&0xf) >= 0x4));
 	if (has_tom2wb)
 		printk(BIOS_DEBUG, "CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB\n");
 
@@ -135,9 +138,8 @@
 	 * undefined side effects.
 	 */
 	msr.lo = msr.hi = 0;
-	for (i = IORR_FIRST; i <= IORR_LAST; i++) {
+	for (i = IORR_FIRST; i <= IORR_LAST; i++)
 		wrmsr(i, msr);
-	}
 
 	/* Enable Variable Mtrrs
 	 * Enable the RdMem and WrMem bits in the fixed mtrrs.
@@ -151,12 +153,12 @@
 
 	enable_cache();
 
-	address_bits = CONFIG_CPU_ADDR_BITS; //K8 could be 40, and GH could be 48
+	//K8 could be 40, and GH could be 48
+	address_bits = CONFIG_CPU_ADDR_BITS;
 
 	/* AMD specific cpuid function to query number of address bits */
-	if (cpuid_eax(0x80000000) >= 0x80000008) {
+	if (cpuid_eax(0x80000000) >= 0x80000008)
 		address_bits = cpuid_eax(0x80000008) & 0xff;
-	}
 
 	/* Now that I have mapped what is memory and what is not
 	 * Set up the mtrrs so we can cache the memory.

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I31b1932a2c1e401e56751e0c790bcc6287fb550d
Gerrit-Change-Number: 20097
Gerrit-PatchSet: 1
Gerrit-Owner: Evelyn Huang <evhuang at google.com>