[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Cache the MMIO BIOS region

[Barnali Sarkar (Code Review)]

Barnali Sarkar has uploaded this change for review. ( https://review.coreboot.org/20089


Change subject: soc/intel/skylake: Cache the MMIO BIOS region
......................................................................

soc/intel/skylake: Cache the MMIO BIOS region

If the boot media is memory mapped temporarily mark it as write
protect MTRR type so that memory-mapped accesses are faster.

Change-Id: Ice217561bb01a43ba520ce51e03d81979f317343
Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
---
M src/soc/intel/skylake/cpu.c
1 file changed, 6 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/20089/1

diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index e85e01f..4554df0 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -567,6 +567,12 @@
 {
 	if (mp_run_on_all_cpus(&x86_setup_mtrrs_with_detect, 1000) < 0)
 		printk(BIOS_ERR, "MTRR programming failure\n");
+
+	/* Temporarily cache the memory-mapped boot media. */
+		if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
+			mtrr_use_temp_range(-CONFIG_ROM_SIZE, CONFIG_ROM_SIZE,
+						MTRR_TYPE_WRPROT);
+
 	x86_mtrr_check();
 }
 

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ice217561bb01a43ba520ce51e03d81979f317343
Gerrit-Change-Number: 20089
Gerrit-PatchSet: 1
Gerrit-Owner: Barnali Sarkar <barnali.sarkar at intel.com>