Hello Rizwan Qureshi,
I'd like you to do a code review. Please visit
https://review.coreboot.org/20054
to review the following change.
Change subject: mb/google/poppy:[WIP] Add camera devices power sequencing through ACPI power resources
......................................................................
mb/google/poppy:[WIP] Add camera devices power sequencing through ACPI power resources
This patch controls the camera devices power through ACPI power resource.
* Add Opregions for PMIC,
* TI_PMIC_POWER_OPREGION
* TI_PMIC_VR_VAL_OPREGION
* TI_PMIC_CLK_OPREGION
* TI_PMIC_CLK_FREQ_OPREGION
* Add power resources for sensors and VCM,
* OVTH for CAM0
* OVFI for CAM1
* VCMP for VCM
* Implement _ON and _OFF methods for senor and VCM module's power on
and power off sequences.
Change-Id: I87cd0508ed5ed922211a51f43ee96b6f44cf673d
Signed-off-by: V Sowmya <v.sowmya at intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
---
M src/mainboard/google/poppy/acpi/mipi_camera.asl
1 file changed, 411 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/20054/1
diff --git a/src/mainboard/google/poppy/acpi/mipi_camera.asl b/src/mainboard/google/poppy/acpi/mipi_camera.asl
index 3806ec8..1a7a98e 100644
--- a/src/mainboard/google/poppy/acpi/mipi_camera.asl
+++ b/src/mainboard/google/poppy/acpi/mipi_camera.asl
@@ -26,6 +26,349 @@
Return (0x0F)
}
+ /* Marks the availability of the region */
+ Name (AVBL, Zero)
+ Method (_REG, 2, NotSerialized)
+ {
+ If (LEqual (Arg0, 0x08))
+ {
+ Store (Arg1, AVBL)
+ }
+ }
+
+ OperationRegion (GPOP, GeneralPurposeIo, 0, 0x2)
+ Name (_CRS, ResourceTemplate ()
+ {
+ I2cSerialBus (0x004D, ControllerInitiated, 0x00061A80,
+ AddressingMode7Bit, "\\_SB.PCI0.I2C2",
+ 0x00, ResourceConsumer, ,
+ )
+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000,
+ IoRestrictionOutputOnly, "\\_SB.PCI0.I2C2.PMIC",
+ 0x00, ResourceConsumer,,)
+ {
+ 4
+ }
+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000,
+ IoRestrictionOutputOnly, "\\_SB.PCI0.I2C2.PMIC",
+ 0x00, ResourceConsumer,,)
+ {
+ 5
+ }
+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000,
+ IoRestrictionOutputOnly, "\\_SB.PCI0.I2C2.PMIC",
+ 0x00, ResourceConsumer,,)
+ {
+ 9
+ }
+ })
+
+ /* PMIC operation regions */
+ /* 0xB0 == TI_PMIC_POWER_OPREGION_ID */
+ OperationRegion (PWR1, 0xB0, Zero, 0x0100)
+ Field(PWR1, DWordAcc, NoLock, Preserve)
+ {
+ VSIO, 32,
+ VCMC, 32,
+ VAX1, 32,
+ VAX2, 32,
+ VACT, 32,
+ VDCT, 32,
+ }
+
+ /* 0xB1 == TI_PMIC_VR_VAL_OPREGION_ID */
+ OperationRegion (PWR2, 0xB1, Zero, 0x0100)
+ Field(PWR2, DWordAcc, NoLock, Preserve)
+ {
+ SIOV, 32,
+ IOVA, 32,
+ VCMV, 32,
+ AX1V, 32,
+ AX2V, 32,
+ ACVA, 32,
+ DCVA, 32,
+ }
+
+ /* 0xB2 == TI_PMIC_CLK_OPREGION_ID */
+ OperationRegion (CLKC, 0xB2, Zero, 0x0100)
+ Field(CLKC, DWordAcc, NoLock, Preserve)
+ {
+ PCTL, 32,
+ PCT2, 32,
+ CFG1, 32,
+ CFG2, 32,
+ }
+
+ /* 0xB3 == TI_PMIC_CLK_FREQ_OPREGION_ID */
+ OperationRegion (CLKF, 0xB3, Zero, 0x0100)
+ Field(CLKF, DWordAcc, NoLock, Preserve)
+ {
+ PDV2, 32,
+ BODI, 32,
+ BUDI, 32,
+ PSWR, 32,
+ XTDV, 32,
+ PLDV, 32,
+ PODV, 32,
+ }
+
+ /* CLE0 and CLE1 are used to determine if both the are
+ enabled are disabled. */
+ Mutex(MUTC, 0)
+ Name (CLE0, 0)
+ Name (CLE1, 0)
+ Method (CLKE, 0, Serialized){
+ Store(0, Local0)
+ /* save Acquire result so we can check for
+ Mutex acquired */
+ Store (Acquire(MUTC, 1000), Local0)
+ /* check for Mutex acquired */
+ If (LEqual(Local0, Zero)) {
+ /* Enable clocks only when a sensor is turned on and
+ both the clocks are disabled */
+ If (LNot(LOr(CLE0, CLE1))) {
+ BODI = 3
+ BUDI = 2
+ PSWR = 19
+ XTDV = 170
+ PLDV = 32
+ PODV = 1
+ PDV2 = 1
+ /* Enable clocks for both the sensors */
+ CFG2 = 5
+ CFG1 = 10
+ PCTL = 209
+ Sleep(1)
+ }
+ Release(MUTC)
+ }
+ }
+
+ /* Clocks need to be disabled only if both the sensors are
+ turned off */
+ Method (CLKD, 0, Serialized) {
+ OR (CLE0, CLE1, Local0)
+ If (LNot(Local0)) {
+ BODI = 0
+ BUDI = 0
+ PSWR = 0
+ XTDV = 0
+ PLDV = 0
+ PODV = 0
+ PDV2 = 0
+ /* Disable clocks for both the sensors */
+ CFG2 = 0
+ CFG1 = 0
+ PCTL = 0
+ }
+ }
+
+ /* Reference count for VSIO */
+ Mutex(MUTV, 0)
+ Name (VSIC, 0)
+ Method (DOVD, 1, Serialized){
+ Store(0, Local0)
+ /* Save Acquire result so we can check for
+ Mutex acquired */
+ Store (Acquire(MUTV, 1000), Local0)
+ /* Check for Mutex acquired */
+ If (LEqual(Local0, Zero)) {
+ /* Turn off VSIO */
+ If (LEqual(Arg0, Zero)) {
+ /* Decrement only if VSIC > 0 */
+ if (LGreater(VSIC, 0)) {
+ Decrement(VSIC)
+ If (LEqual(VSIC, Zero)) {
+ VSIO = 0
+ }
+ }
+ } ElseIf (LEqual(Arg0, 2)) {
+ /* Increment only if VSIC < 2 */
+ If (LLess(VSIC, 2)) {
+ /* Turn on VSIO */
+ If (LEqual(VSIC, Zero)) {
+ VSIO = 3
+ }
+ Increment(VSIC)
+ }
+ }
+
+ Release(MUTV)
+ }
+ }
+
+ /* Power resource methods for CAM0 */
+ PowerResource (OVTH, 0, 0) {
+ Name (STA, 0)
+ Method (_ON, 0, Serialized) {
+ If (LEqual (AVBL, 1)) {
+ If (LEqual (STA, 0)) {
+ /* Enable VSIO regulator +
+ daisy chain */
+ DOVD(1)
+
+ if (LNotEqual(IOVA, 52)) {
+ /* Set VSIO value as 1.8006 V */
+ IOVA = 52
+ }
+ if (LNotEqual(SIOV, 52)) {
+ /* Set VSIO value as 1.8006 V */
+ SIOV = 52
+ }
+ Sleep(3)
+
+ VACT = 1
+ if (LNotEqual(ACVA, 109)) {
+ /* Set ANA at 2.8152V */
+ ACVA = 109
+ }
+ Sleep(3)
+
+ \_SB.PCI0.I2C2.PMIC.CLKE()
+ CLE0 = 1
+
+ VDCT = 1
+ if (LNotEqual(DCVA, 12)) {
+ DCVA = 12 /* Set CORE at 1.2V */
+ }
+ Sleep(3)
+ \_SB.PCI0.I2C2.CAM0.CRST(1)
+
+ STA = 1
+ }
+ }
+ }
+
+ Method (_OFF, 0, Serialized) {
+ If (LEqual (AVBL, 1)) {
+ If (LEqual (STA, 1)) {
+ Sleep(2)
+ CLE0 = 0
+ \_SB.PCI0.I2C2.PMIC.CLKD()
+ Sleep(2)
+ \_SB.PCI0.I2C2.CAM0.CRST(0)
+ Sleep(3)
+ VDCT = 0
+ Sleep(3)
+ VACT = 0
+ Sleep(1)
+ DOVD(0)
+ Sleep(1)
+ }
+ }
+ STA = 0
+ }
+ Method (_STA, 0, NotSerialized) {
+ Return (STA)
+ }
+ }
+
+ /* Power resource methods for CAM1 */
+ PowerResource (OVFI, 0, 0) {
+ Name (STA, 0)
+ Method (_ON, 0, Serialized) {
+ If (LEqual (AVBL, 1)) {
+ If (LEqual (STA, 0)) {
+ VAX2 = 1 /* Enable VAUX2 */
+
+ if (LNotEqual(AX2V, 52)) {
+ /* Set VAUX2 as 1.8006 V */
+ AX2V = 52
+ }
+ Sleep(1)
+
+ \_SB.PCI0.I2C2.PMIC.CLKE()
+ CLE1 = 1
+
+ VAX1 = 1 /* Enable VAUX1 */
+ if (LNotEqual(AX1V, 19)) {
+ /* Set VAUX1 as 1.2132 V */
+ AX1V = 19
+ }
+ Sleep(3)
+
+ \_SB.PCI0.I2C4.CAM1.CGP4(1)
+ Sleep(3)
+
+ \_SB.PCI0.I2C4.CAM1.CGP5(1)
+ Sleep(3)
+ STA = 1
+ }
+ }
+ }
+
+ Method (_OFF, 0, Serialized) {
+ If (LEqual (AVBL, 1)) {
+ If (LEqual (STA, 1)) {
+ Sleep(2)
+ CLE1 = 0
+ \_SB.PCI0.I2C2.PMIC.CLKD()
+ Sleep(2)
+ \_SB.PCI0.I2C4.CAM1.CGP5(0)
+ Sleep(3)
+ VAX1 = 0
+ Sleep(1)
+ \_SB.PCI0.I2C4.CAM1.CGP4(0)
+ Sleep(1)
+ VAX2 = 0
+ Sleep(1)
+
+ }
+ STA = 0
+ }
+ }
+ Method (_STA, 0, NotSerialized) {
+ Return (STA)
+ }
+ }
+
+ /* Power resource methods for VCM */
+ PowerResource (VCMP, 0, 0) {
+ Name (STA, 0)
+ Method (_ON, 0, Serialized) {
+ If (LEqual (AVBL, 1)) {
+ If (LEqual (STA, 0)) {
+ /* Enable VSIO regulator +
+ daisy chain */
+ DOVD(1)
+ if (LNotEqual(IOVA, 52)) {
+ /* Set VSIO value as 1.8006 V */
+ IOVA = 52
+ }
+ if (LNotEqual(SIOV, 52)) {
+ /* Set VSIO value as 1.8006 V */
+ SIOV = 52
+ }
+ Sleep(3)
+
+ VCMC = 1 /* Enable VCM regulator */
+ if (LNotEqual(VCMV, 109)) {
+ /* Set VCM value at 2.8152 V */
+ VCMV = 109
+ }
+ Sleep(3)
+
+ STA = 1
+ }
+ }
+ }
+ Method (_OFF, 0, Serialized) {
+ If (LEqual (AVBL, 1)) {
+ If (LEqual (STA, 1)) {
+ VCMC = 0 /* Disable regulator */
+ Sleep(1)
+ DOVD(0) /* Disable regulator */
+ Sleep(1)
+ STA = 0
+ }
+ }
+ }
+
+ Method (_STA, 0, NotSerialized) {
+ Return (STA)
+ }
+ }
+
}
}
@@ -52,6 +395,31 @@
0x00, ResourceConsumer, ,
)
})
+
+ Field (\_SB.PCI0.I2C2.PMIC.GPOP, ByteAcc, NoLock, Preserve)
+ {
+ Connection
+ (
+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000,
+ IoRestrictionOutputOnly,
+ "\\_SB.PCI0.I2C2.PMIC", 0x00,
+ ResourceConsumer,,)
+ {
+ 9
+ }
+ ),
+ GRST, 1,
+ }
+
+ /* Set or clear GRST GPIO */
+ Method (CRST, 1, Serialized)
+ {
+ GRST = Arg0
+ }
+
+ Name (_PR0, Package () { ^^I2C2.PMIC.OVTH })
+ Name (_PR3, Package () { ^^I2C2.PMIC.OVTH })
+
/* Port0 of CAM0 is connected to port0 of CIO2 device */
Name (_DSD, Package () {
@@ -135,6 +503,8 @@
)
})
+ Name (_PR0, Package () { ^PMIC.VCMP })
+ Name (_PR3, Package () { ^PMIC.VCMP })
}
}
@@ -162,6 +532,47 @@
)
})
+ Field (\_SB.PCI0.I2C2.PMIC.GPOP, ByteAcc, NoLock, Preserve)
+ {
+ Connection
+ (
+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000,
+ IoRestrictionOutputOnly,
+ "\\_SB.PCI0.I2C2.PMIC", 0x00,
+ ResourceConsumer,,)
+ {
+ 4
+ }
+ ),
+ GPO4, 1,
+ Connection
+ (
+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000,
+ IoRestrictionOutputOnly,
+ "\\_SB.PCI0.I2C2.PMIC", 0x00,
+ ResourceConsumer,,)
+ {
+ 5
+ }
+ ),
+ GPO5, 1,
+ }
+
+ /* Set or clear GPO4 GPIO */
+ Method (CGP4, 1, Serialized)
+ {
+ GPO4 = Arg0
+ }
+
+ /* Set or clear GPO5 GPIO */
+ Method (CGP5, 1, Serialized)
+ {
+ GPO5 = Arg0
+ }
+
+ Name (_PR0, Package () { ^^I2C2.PMIC.OVFI })
+ Name (_PR3, Package () { ^^I2C2.PMIC.OVFI })
+
/* Port0 of CAM1 is connected to port1 of CIO2 device */
Name (_DSD, Package () {
ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
--
To view, visit https://review.coreboot.org/20054
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I87cd0508ed5ed922211a51f43ee96b6f44cf673d
Gerrit-Change-Number: 20054
Gerrit-PatchSet: 1
Gerrit-Owner: V Sowmya <v.sowmya at intel.com>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani at intel.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>