[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add Makefile

[Andrey Petrov (Code Review)]

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/20073


Change subject: soc/intel/cannonlake: Add Makefile
......................................................................

soc/intel/cannonlake: Add Makefile

This enables building working bootblock and non-functional romstage
and ramstage.

Change-Id: I580cd2c3279d742f202b2adfbe55c814cfb48f99
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
M src/soc/intel/cannonlake/Makefile.inc
1 file changed, 20 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/20073/1

diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 4651a23..a0d27c0 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -1,7 +1,27 @@
 ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y)
 
+subdirs-y += ../../../cpu/x86/mtrr
+subdirs-y += ../../../cpu/x86/tsc
+
+bootblock-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
+bootblock-y += bootblock/bootblock.c
+bootblock-y += bootblock/cpu.c
+bootblock-y += bootblock/pch.c
+bootblock-y += bootblock/report_platform.c
+bootblock-y += gpio_private.c
+bootblock-y += tsc_freq.c
+
 romstage-y += cbmem.c
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
 
 ramstage-y += cbmem.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
+ramstage-y += tsc_freq.c
+
+CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20
+CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cannonlake
+
+CPPFLAGS_common += -I$(src)/soc/intel/cannonlake
+CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include
 
 endif

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I580cd2c3279d742f202b2adfbe55c814cfb48f99
Gerrit-Change-Number: 20073
Gerrit-PatchSet: 1
Gerrit-Owner: Andrey Petrov <andrey.petrov at intel.com>