[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add UART initialization

[Andrey Petrov (Code Review)]

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/20063


Change subject: soc/intel/cannonlake: Add UART initialization
......................................................................

soc/intel/cannonlake: Add UART initialization

Cannonlake has built-in UART driver as part of LPSS block. However port
mapped decoders are in use as well.

Change-Id: I9f209bf29c1748c5beea31bc6b31cb07a1e14195
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
A src/soc/intel/cannonlake/uart.c
1 file changed, 61 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/20063/1

diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c
new file mode 100644
index 0000000..8e33d77
--- /dev/null
+++ b/src/soc/intel/cannonlake/uart.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2017 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/uart.h>
+#include <device/pci_def.h>
+#include <intelblocks/gpio.h>
+#include <intelblocks/lpss.h>
+#include <intelblocks/pcr.h>
+#include <intelblocks/uart.h>
+#include <soc/bootblock.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <soc/iomap.h>
+
+/* Serial IO UART controller legacy mode */
+#define PCR_SERIAL_IO_GPPRVRW7		0x618
+#define PCR_SIO_PCH_LEGACY_UART0	(1 << 0)
+#define PCR_SIO_PCH_LEGACY_UART1	(1 << 1)
+#define PCR_SIO_PCH_LEGACY_UART2	(1 << 2)
+
+/* Clock divider parameters for 115200 baud rate */
+#define CLK_M_VAL	0x30
+#define CLK_N_VAL	0xc35
+
+/* UART2 pad configuration. Support RXD and TXD for now. */
+static const struct pad_config uart2_pads[] = {
+/* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+/* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+};
+
+void pch_uart_init(void)
+{
+	uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
+
+	uart_common_init(PCH_DEV_UART2, base, CLK_M_VAL, CLK_N_VAL);
+
+	/* Put UART2 in byte access mode for 16550 compatibility */
+	pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
+		PCR_SIO_PCH_LEGACY_UART2);
+	gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+uintptr_t uart_platform_base(int idx)
+{
+	/* Same base address for all debug port usage. In reality UART2
+	 * is currently only supported. */
+	return UART_DEBUG_BASE_ADDRESS;
+}

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9f209bf29c1748c5beea31bc6b31cb07a1e14195
Gerrit-Change-Number: 20063
Gerrit-PatchSet: 1
Gerrit-Owner: Andrey Petrov <andrey.petrov at intel.com>