[coreboot-gerrit] Change in coreboot[master]: soc/braswell: fix ACPI table by recollecting TOLM

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/20060


Change subject: soc/braswell: fix ACPI table by recollecting TOLM
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soc/braswell: fix ACPI table by recollecting TOLM

cherry-pick from Chromium, commit 8fbe1e7

On Braswell and Baytrail devices, by userland 'perf top',
observed demanding clocks on __vdso_clock_gettime() since
chromeos_3.18 kernel; besides, evaluated massive calling of
clock_gettime() cost, up to 700 ns in average.

It turns out that Linux kernel of map_vdso() first call of
remap_pfn_range() does not fall into reserve_pfn_range()
due to size parameter, instead it relies on lookup_memtype()
and potentially be failed to be identified as eligible RAM
resource because the function of pat_pagerange_is_ram() actually
walks through root's sibling.

Meanwhile, on current BSW (and BYT) firmware implementation
makes System RAM resources located on child leaf, combining all
of these factors makes the kernel treat the vvar page of vdso
as a uncached-minus one leading slow access in result.

This patch recollects TOLM accessing; as Aaron recalled some
core_msr_script turns off access to TOLM register, he suggests
to store tolm to avoid getting back a zero while setting acpi
nvs space.

Original-Change-Id: Iad4ffa542b22073cb087100a95169e2d2a52efcd
Original-Signed-off-by: Harry Pan <harry.pan at intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/368585
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>

Change-Id: Idc9765ec5c0920dc98baeb9267a89bec5cadd5a0
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/soc/intel/braswell/northcluster.c
1 file changed, 9 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/20060/1

diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c
index 404a8f1..dc72a46 100644
--- a/src/soc/intel/braswell/northcluster.c
+++ b/src/soc/intel/braswell/northcluster.c
@@ -29,6 +29,7 @@
 #include <soc/ramstage.h>
 #include <soc/smm.h>
 #include <vendorcode/google/chromeos/chromeos.h>
+#include <stddef.h>
 
 /*
  * Host Memory Map:
@@ -70,7 +71,14 @@
 
 uint32_t nc_read_top_of_low_memory(void)
 {
-	return iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1);
+	MAYBE_STATIC uint32_t tolm = 0;
+
+	if (tolm)
+		return tolm;
+
+	tolm = iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1);
+
+	return tolm;
 }
 
 static void nc_read_resources(device_t dev)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Idc9765ec5c0920dc98baeb9267a89bec5cadd5a0
Gerrit-Change-Number: 20060
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
Gerrit-Reviewer: Harry Pan <harry.pan at intel.com>