[coreboot-gerrit] Change in coreboot[master]: sb/intel/bd82x6x/pcie: Add PCIe reset timeout

[Patrick Rudolph (Code Review)]

Hello Arthur Heymans, build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/20045

to look at the new patch set (#4).

Change subject: sb/intel/bd82x6x/pcie: Add PCIe reset timeout
......................................................................

sb/intel/bd82x6x/pcie: Add PCIe reset timeout

If no device is found, make sure to wait 100msec and scan
bridge again.

May introduce a boot delay of up to 100msec. As timestamps are
used the delay is at maximum 100msec, no matter how many PCIe ports
are there.
The delay is only used in case no device is found. If a device has been
found there's no need to wait.

Fixes a regression introduced by
Change-Id: I6ee5e5f33824acdbca0f6ed28e90beab7fe10002
where a port is disabled as the connected device hasn't powered up yet.

Tested on Lenovo T430.

Change-Id: I990e2577f0acf7d1956b42af2611405f1421e6d3
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
M src/southbridge/intel/bd82x6x/pcie.c
1 file changed, 24 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/20045/4
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I990e2577f0acf7d1956b42af2611405f1421e6d3
Gerrit-Change-Number: 20045
Gerrit-PatchSet: 4
Gerrit-Owner: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>