[coreboot-gerrit] Change in coreboot[master]: Simplify the code of riscv exception handling

[Anonymous Coward (Code Review)]

Anonymous Coward #1001664 has uploaded this change for review. ( https://review.coreboot.org/20046


Change subject: Simplify the code of riscv exception handling
......................................................................

Simplify the code of riscv exception handling

There is some useless code. This code is not necessary.
It's cam be remove. The code will become simple and do
not need to insert the assembly code

Change-Id: I92f7df2202f1c886789a9a29285f4321eec75d23
Signed-off-by: wxjstz <wxjstz at 126.com>
---
M src/arch/riscv/trap_handler.c
M src/arch/riscv/trap_util.S
2 files changed, 4 insertions(+), 23 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/20046/1

diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index 4dd3d5b..0cfd8dc 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -69,7 +69,6 @@
 	}
 	tf->gpr[10] = returnValue;
 	write_csr(mepc, read_csr(mepc) + 4);
-	asm volatile("j supervisor_call_return");
 }
 
 static const char *const exception_names[] = {
@@ -206,6 +205,7 @@
 		case CAUSE_HYPERVISOR_ECALL:
 		case CAUSE_MACHINE_ECALL:
 			print_trap_information(tf);
+			die("Can't recover from trap. Halting.\n");
 			break;
 		case CAUSE_MISALIGNED_LOAD:
 			print_trap_information(tf);
@@ -225,10 +225,10 @@
 			printk(BIOS_EMERG, "Coreboot: can not handle a trap:\n");
 			printk(BIOS_EMERG, "================================\n");
 			print_trap_information(tf);
+			die("Can't recover from trap. Halting.\n");
 			break;
 	}
 
-	die("Can't recover from trap. Halting.\n");
 }
 
 static uint32_t fetch_instruction(uintptr_t vaddr) {
@@ -262,7 +262,6 @@
 
 	// return to where we came from
 	write_csr(mepc, read_csr(mepc) + 4);
-	asm volatile("j machine_call_return");
 }
 
 void handle_misaligned_store(trapframe *tf) {
@@ -290,5 +289,4 @@
 
 	// return to where we came from
 	write_csr(mepc, read_csr(mepc) + 4);
-	asm volatile("j machine_call_return");
 }
diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S
index ae32379..7eb964e 100644
--- a/src/arch/riscv/trap_util.S
+++ b/src/arch/riscv/trap_util.S
@@ -105,17 +105,7 @@
 
   .endm
 
-.globl estack
-  .text
-  .global  supervisor_trap_entry
-supervisor_trap_entry:
-    csrw mscratch, sp
-    # load in the top of the machine stack
-    la	sp, _estack
-    addi sp,sp,-MENTRY_FRAME_SIZE
-    save_tf
-    move  a0,sp
-    jal trap_handler
+
     .global  trap_entry
 trap_entry:
   csrw mscratch, sp
@@ -136,14 +126,7 @@
   save_tf
   move  a0,sp
   jal trap_handler
-  .global supervisor_call_return
-supervisor_call_return:
-  csrr a0, mscratch
-  restore_regs
-  # go back into supervisor call
-  .word 0x30200073 # mret
-  .global machine_call_return
-machine_call_return:
+
     csrr a0, mscratch
     restore_regs
     # go back into machine call

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I92f7df2202f1c886789a9a29285f4321eec75d23
Gerrit-Change-Number: 20046
Gerrit-PatchSet: 1
Gerrit-Owner: Anonymous Coward #1001664