[coreboot-gerrit] Change in coreboot[master]: payloads: change coreboot to lowercase

[Martin Roth (Code Review)]

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20028


Change subject: payloads: change coreboot to lowercase
......................................................................

payloads: change coreboot to lowercase

The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.

Change-Id: I2ec18ca55e0ea672343a951ab81a24a5630f45fd
Signed-off-by: Martin Roth <martinroth at google.com>
---
M payloads/bayou/lzma.c
M payloads/coreinfo/bootlog_module.c
M payloads/coreinfo/coreboot_module.c
M payloads/coreinfo/timestamps_module.c
M payloads/external/SeaBIOS/Kconfig
M payloads/libpayload/arch/arm64/main.c
M payloads/libpayload/libc/malloc.c
7 files changed, 9 insertions(+), 9 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/20028/1

diff --git a/payloads/bayou/lzma.c b/payloads/bayou/lzma.c
index a7a8717..14bd921 100644
--- a/payloads/bayou/lzma.c
+++ b/payloads/bayou/lzma.c
@@ -1,6 +1,6 @@
 /*
 
-Coreboot interface to memory-saving variant of LZMA decoder
+coreboot interface to memory-saving variant of LZMA decoder
 
 (C)opyright 2006 Carl-Daniel Hailfinger
 Released under the GNU GPL v2 or later
diff --git a/payloads/coreinfo/bootlog_module.c b/payloads/coreinfo/bootlog_module.c
index b3f0dee..8a9e7a3 100644
--- a/payloads/coreinfo/bootlog_module.c
+++ b/payloads/coreinfo/bootlog_module.c
@@ -170,7 +170,7 @@
 
 static int bootlog_module_redraw(WINDOW *win)
 {
-	print_module_title(win, "Coreboot Bootlog");
+	print_module_title(win, "coreboot Bootlog");
 
 	if (!g_buf) {
 		return -1;
diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c
index 0b6cca8..adf8f14 100644
--- a/payloads/coreinfo/coreboot_module.c
+++ b/payloads/coreinfo/coreboot_module.c
@@ -42,10 +42,10 @@
 	int row = 2;
 	int i;
 
-	print_module_title(win, "Coreboot Tables");
+	print_module_title(win, "coreboot Tables");
 
 	if (tables_good) {
-		mvwprintw(win, row++, 1, "No Coreboot tables were found");
+		mvwprintw(win, row++, 1, "No coreboot tables were found");
 		return 0;
 	}
 
@@ -249,7 +249,7 @@
 }
 
 struct coreinfo_module coreboot_module = {
-	.name = "Coreboot",
+	.name = "coreboot",
 	.init = coreboot_module_init,
 	.redraw = coreboot_module_redraw,
 };
diff --git a/payloads/coreinfo/timestamps_module.c b/payloads/coreinfo/timestamps_module.c
index eedb3c9..020fcc6 100644
--- a/payloads/coreinfo/timestamps_module.c
+++ b/payloads/coreinfo/timestamps_module.c
@@ -228,7 +228,7 @@
 
 static int timestamps_module_redraw(WINDOW *win)
 {
-	print_module_title(win, "Coreboot Timestamps");
+	print_module_title(win, "coreboot Timestamps");
 
 	if (!g_buf)
 		return -1;
diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig
index b0fb1a5..dc04f37 100644
--- a/payloads/external/SeaBIOS/Kconfig
+++ b/payloads/external/SeaBIOS/Kconfig
@@ -57,7 +57,7 @@
 	depends on !VGA_BIOS && MAINBOARD_DO_NATIVE_VGA_INIT
 	bool
 	help
-	  Coreboot can initialize the GPU of some mainboards.
+	  coreboot can initialize the GPU of some mainboards.
 
 	  After initializing the GPU, the information about it can be passed to the payload.
 	  Provide an option rom that implements this legacy VGA BIOS compatibility requirement.
diff --git a/payloads/libpayload/arch/arm64/main.c b/payloads/libpayload/arch/arm64/main.c
index e616956..aa2292f 100644
--- a/payloads/libpayload/arch/arm64/main.c
+++ b/payloads/libpayload/arch/arm64/main.c
@@ -64,7 +64,7 @@
 	mmu_presysinfo_memory_used(start, end - start);
 
 	/*
-	 * Memory range 2: Coreboot tables
+	 * Memory range 2: coreboot tables
 	 *
 	 * Maximum size is assumed 2 pages in case it crosses the GRANULE_SIZE
 	 * boundary
diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c
index b7ac1a7..595af63 100644
--- a/payloads/libpayload/libc/malloc.c
+++ b/payloads/libpayload/libc/malloc.c
@@ -94,7 +94,7 @@
 	}
 
 	/*
-	 * DMA memory might not be zeroed by Coreboot on stage loading, so make
+	 * DMA memory might not be zeroed by coreboot on stage loading, so make
 	 * sure we clear the magic cookie from last boot.
 	 */
 	*(hdrtype_t *)start = 0;

-- 
To view, visit https://review.coreboot.org/20028
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2ec18ca55e0ea672343a951ab81a24a5630f45fd
Gerrit-Change-Number: 20028
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>