[coreboot-gerrit] Change in coreboot[master]: src: change coreboot to lowercase
Martin Roth (Code Review)
gerrit at coreboot.org
Sun Jun 4 05:28:02 CEST 2017
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20029
Change subject: src: change coreboot to lowercase
......................................................................
src: change coreboot to lowercase
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.
Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2
Signed-off-by: Martin Roth <martinroth at google.com>
---
M src/arch/riscv/sbi.S
M src/arch/riscv/trap_handler.c
M src/cpu/amd/car/cache_as_ram.inc
M src/cpu/amd/family_10h-family_15h/fidvid.c
M src/cpu/amd/quadcore/quadcore_id.c
M src/drivers/aspeed/common/ast_dp501.c
M src/drivers/aspeed/common/ast_dram_tables.h
M src/drivers/intel/fsp1_1/cache_as_ram.inc
M src/drivers/intel/fsp1_1/raminit.c
M src/drivers/xgi/common/XGI_main.h
M src/drivers/xgi/common/vb_init.c
M src/drivers/xgi/common/vb_setmode.c
M src/drivers/xgi/common/vb_util.c
M src/ec/quanta/ene_kb3940q/acpi/ec.asl
M src/include/console/post_codes.h
M src/include/memrange.h
M src/include/types.h
M src/lib/selfboot.c
M src/mainboard/amd/inagua/broadcom.c
M src/mainboard/pcengines/alix2d/romstage.c
M src/northbridge/via/vx900/early_vx900.c
M src/soc/intel/apollolake/acpi/globalnvs.asl
M src/soc/intel/apollolake/include/soc/nvs.h
M src/soc/intel/broadwell/acpi/globalnvs.asl
M src/soc/intel/broadwell/include/soc/nvs.h
M src/soc/intel/skylake/acpi/globalnvs.asl
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/cpu.c
M src/soc/intel/skylake/include/soc/nvs.h
M src/soc/samsung/exynos5250/alternate_cbfs.c
M src/soc/samsung/exynos5420/alternate_cbfs.c
M src/soc/samsung/exynos5420/smp.c
M src/southbridge/intel/common/firmware/Makefile.inc
M src/vendorcode/amd/cimx/sb700/SBCMN.c
M src/vendorcode/amd/cimx/sb700/SBPort.c
35 files changed, 37 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/20029/1
diff --git a/src/arch/riscv/sbi.S b/src/arch/riscv/sbi.S
index 0ff7c3b..608afc3 100644
--- a/src/arch/riscv/sbi.S
+++ b/src/arch/riscv/sbi.S
@@ -58,7 +58,7 @@
.align 4
/* -1984: int sbi_console_getchar(void); */
- li a0, -1 /* failure: Coreboot doesn't support console input */
+ li a0, -1 /* failure: coreboot doesn't support console input */
jr ra
.align 4
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index 4dd3d5b..ca4954f 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -180,7 +180,7 @@
break;
default:
printk(BIOS_EMERG, "======================================\n");
- printk(BIOS_EMERG, "Coreboot: Unknown machine interrupt: 0x%llx\n",
+ printk(BIOS_EMERG, "coreboot: Unknown machine interrupt: 0x%llx\n",
cause);
printk(BIOS_EMERG, "======================================\n");
print_trap_information(tf);
@@ -222,7 +222,7 @@
break;
default:
printk(BIOS_EMERG, "================================\n");
- printk(BIOS_EMERG, "Coreboot: can not handle a trap:\n");
+ printk(BIOS_EMERG, "coreboot: can not handle a trap:\n");
printk(BIOS_EMERG, "================================\n");
print_trap_information(tf);
break;
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 5305603..47031a6 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -45,7 +45,7 @@
* xmm2: Fam10h comparison value
* xmm3: Fam15h comparison value
* xmm4: Backup EBX
- * xmm5: Coreboot init detect
+ * xmm5: coreboot init detect
*/
/* Save the BIST result. */
diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c
index 8fe708c..1262718 100644
--- a/src/cpu/amd/family_10h-family_15h/fidvid.c
+++ b/src/cpu/amd/family_10h-family_15h/fidvid.c
@@ -60,7 +60,7 @@
by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required
if the warm reset is issued by coreboot to update NbFid. So it is required
or not ? How can I tell who issued warm reset ?
- Coreboot transitions to P0 instead, which is not recommended, and does
+ coreboot transitions to P0 instead, which is not recommended, and does
not follow 2.4.2.15.2 to do so.
9.- TODO Requires information on current delivery capability
diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c
index cd83906..9892c12 100644
--- a/src/cpu/amd/quadcore/quadcore_id.c
+++ b/src/cpu/amd/quadcore/quadcore_id.c
@@ -105,7 +105,7 @@
}
}
if (fam15h && dual_node) {
- /* Coreboot expects each separate processor die to be on a different nodeid.
+ /* coreboot expects each separate processor die to be on a different nodeid.
* Since the code above returns nodeid 0 even on internal node 1 some fixup is needed...
*/
uint32_t f5x84;
@@ -123,7 +123,7 @@
id.coreid = id.coreid - core_count;
}
} else if (rev_gte_d && dual_node) {
- /* Coreboot expects each separate processor die to be on a different nodeid.
+ /* coreboot expects each separate processor die to be on a different nodeid.
* Since the code above returns nodeid 0 even on internal node 1 some fixup is needed...
*/
uint8_t core_count = (((f3xe8 & 0x00008000) >> 13) | ((f3xe8 & 0x00003000) >> 12)) + 1;
diff --git a/src/drivers/aspeed/common/ast_dp501.c b/src/drivers/aspeed/common/ast_dp501.c
index 448899e..46b76f5 100644
--- a/src/drivers/aspeed/common/ast_dp501.c
+++ b/src/drivers/aspeed/common/ast_dp501.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* File taken from the Linux ast driver (v3.18.5)
- * Coreboot-specific includes added at top and/or contents modified
+ * coreboot-specific includes added at top and/or contents modified
* as needed to function within the coreboot environment.
*
* This program is free software; you can redistribute it and/or modify
diff --git a/src/drivers/aspeed/common/ast_dram_tables.h b/src/drivers/aspeed/common/ast_dram_tables.h
index fbef1e9..1d46ca6 100644
--- a/src/drivers/aspeed/common/ast_dram_tables.h
+++ b/src/drivers/aspeed/common/ast_dram_tables.h
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* File taken from the Linux ast driver (v3.18.5)
- * Coreboot-specific includes added at top and/or contents modified
+ * coreboot-specific includes added at top and/or contents modified
* as needed to function within the coreboot environment.
*
* This program is free software; you can redistribute it and/or modify
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc
index 6611fa1..fc66208 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc
@@ -137,7 +137,7 @@
/* Save FSP_INFO_HEADER location in ebx */
mov %ebp, %ebx
- /* Coreboot assumes stack/heap region will be zero */
+ /* coreboot assumes stack/heap region will be zero */
cld
movl %ecx, %edi
neg %ecx
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 6e2efcf..5b6ec9e 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -277,7 +277,7 @@
/* Verify the FSP 1.1 HOB interface */
if (fsp_verification_failure)
- die("ERROR - Coreboot's requirements not met by FSP binary!\n");
+ die("ERROR - coreboot's requirements not met by FSP binary!\n");
/* Display the memory configuration */
report_memory_config();
diff --git a/src/drivers/xgi/common/XGI_main.h b/src/drivers/xgi/common/XGI_main.h
index 39d7ec8..52421e9 100644
--- a/src/drivers/xgi/common/XGI_main.h
+++ b/src/drivers/xgi/common/XGI_main.h
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* File taken from the Linux xgifb driver (v3.18.5)
- * Coreboot-specific includes added at top
+ * coreboot-specific includes added at top
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/drivers/xgi/common/vb_init.c b/src/drivers/xgi/common/vb_init.c
index 4070e4e..bc66bda 100644
--- a/src/drivers/xgi/common/vb_init.c
+++ b/src/drivers/xgi/common/vb_init.c
@@ -4,7 +4,7 @@
* Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
*
* File taken from the Linux xgifb driver (v3.18.5)
- * Coreboot-specific includes added at top
+ * coreboot-specific includes added at top
* XGINew_SetDRAMSize_340 slightly modified for coreboot text mode
*
* This program is free software; you can redistribute it and/or modify
diff --git a/src/drivers/xgi/common/vb_setmode.c b/src/drivers/xgi/common/vb_setmode.c
index 0143076..1678b75 100644
--- a/src/drivers/xgi/common/vb_setmode.c
+++ b/src/drivers/xgi/common/vb_setmode.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* File taken from the Linux xgifb driver (v3.18.5)
- * Coreboot-specific includes added at top
+ * coreboot-specific includes added at top
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/drivers/xgi/common/vb_util.c b/src/drivers/xgi/common/vb_util.c
index 19c29a1..f71ad56 100644
--- a/src/drivers/xgi/common/vb_util.c
+++ b/src/drivers/xgi/common/vb_util.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* File taken from the Linux xgifb driver (v3.18.5)
- * Coreboot-specific includes added at top
+ * coreboot-specific includes added at top
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/ec/quanta/ene_kb3940q/acpi/ec.asl b/src/ec/quanta/ene_kb3940q/acpi/ec.asl
index 251b450..70f1366 100644
--- a/src/ec/quanta/ene_kb3940q/acpi/ec.asl
+++ b/src/ec/quanta/ene_kb3940q/acpi/ec.asl
@@ -63,7 +63,7 @@
BTBD, 1, // Battery Malfunction ; 70h.3
ACMD, 1, // ACPI Mode ; 70h.4
, 1, // Reserved ; 70h.5
- SSBS, 1, // 1=Standard BIOS, 0=Coreboot ; 70h.6
+ SSBS, 1, // 1=Standard BIOS, 0=coreboot ; 70h.6
PSTH, 1, // Passive Thermal Policy ; 70h.7
BST0, 8, // Battery Status ; 71h
// Bit0 : Discharging
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index f08796c..1368aa8 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -329,7 +329,7 @@
/**
* \brief Elfload fail or die() called
*
- * Coreboot was not able to load the payload, no payload was detected
+ * coreboot was not able to load the payload, no payload was detected
* or die() was called.
* \n
* If this code appears before entering ramstage, then most likely
diff --git a/src/include/memrange.h b/src/include/memrange.h
index bf6b8e4..46a992a 100644
--- a/src/include/memrange.h
+++ b/src/include/memrange.h
@@ -21,7 +21,7 @@
* is exposed so that a memranges can be used on the stack if needed. */
struct memranges {
struct range_entry *entries;
- /* Coreboot doesn't have a free() function. Therefore, keep a cache of
+ /* coreboot doesn't have a free() function. Therefore, keep a cache of
* free'd entries. */
struct range_entry *free_list;
};
diff --git a/src/include/types.h b/src/include/types.h
index a4d8224..df09473 100644
--- a/src/include/types.h
+++ b/src/include/types.h
@@ -26,7 +26,7 @@
#define BIT(x) (1ul << (x))
/**
- * Coreboot error codes
+ * coreboot error codes
*
* When building functions that return a status or an error code, use cb_err as
* the return type. When failure reason needs to be communicated by the return
diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c
index ef1b986..160e8f5 100644
--- a/src/lib/selfboot.c
+++ b/src/lib/selfboot.c
@@ -73,7 +73,7 @@
*
* Benefits:
* - Nearly arbitrary standalone executables can be loaded.
- * - Coreboot is preserved, so it can be returned to.
+ * - coreboot is preserved, so it can be returned to.
* - The implementation is still relatively simple,
* and much simpler than the general case implemented in kexec.
*/
diff --git a/src/mainboard/amd/inagua/broadcom.c b/src/mainboard/amd/inagua/broadcom.c
index 640f639..9f140a2 100644
--- a/src/mainboard/amd/inagua/broadcom.c
+++ b/src/mainboard/amd/inagua/broadcom.c
@@ -26,7 +26,7 @@
#include <types.h>
#include <console/console.h>
-#include <device/device.h> //Coreboot device access
+#include <device/device.h> //coreboot device access
#include <device/pci.h>
#include <delay.h>
#include <endian.h>
diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c
index ab96dd2..c7bf9ef 100644
--- a/src/mainboard/pcengines/alix2d/romstage.c
+++ b/src/mainboard/pcengines/alix2d/romstage.c
@@ -105,7 +105,7 @@
* Info: GPIO_IO_BASE, 0x6100, is only valid before PCI init, so it
* may be used here, but not after PCI Init.
* Note: Prior to a certain release, Linux used a hardwired 0x6100 in the
- * leds-alix2.c driver. Coreboot dynamically assigns this space,
+ * leds-alix2.c driver. coreboot dynamically assigns this space,
* so the driver does not work anymore.
* Good workaround: use the newer driver
* Ugly workaround: $ wrmsr 0x5140000C 0xf00100006100
diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c
index b350ffd..54a30af 100644
--- a/src/northbridge/via/vx900/early_vx900.c
+++ b/src/northbridge/via/vx900/early_vx900.c
@@ -102,7 +102,7 @@
* \brief Disables 'shadowing' of system ROM
*
* Disable unnecessary shadowing of the ROM in the first 1MB of address space.
- * Coreboot runs in 32-bit mode from the start. Shadowing only gets in the way.
+ * coreboot runs in 32-bit mode from the start. Shadowing only gets in the way.
* This function frees the entire 640k-1M range for DRAM. VGA may still use
* the 640k-768k range, if enabled later.
*/
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index bdba305..1548c30 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -33,7 +33,7 @@
LIDS, 8, // 0x02 - LID State
PWRS, 8, // 0x03 - AC Power State
DPTE, 8, // 0x04 - Enable DPTF
- CBMC, 32, // 0x05 - 0x08 - Coreboot Memory Console
+ CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console
PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index
GPEI, 64, // 0x11 - 0x18 - GPE Wake Source
NHLA, 64, // 0x19 - 0x20 - NHLT Address
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index f9cc49d..e0b223f 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -33,7 +33,7 @@
uint8_t lids; /* 0x02 - LID State */
uint8_t pwrs; /* 0x03 - AC Power State */
uint8_t dpte; /* 0x04 - Enable DPTF */
- uint32_t cbmc; /* 0x05 - 0x08 - Coreboot Memory Console */
+ uint32_t cbmc; /* 0x05 - 0x08 - coreboot Memory Console */
uint64_t pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
uint64_t gpei; /* 0x11 - 0x18 - GPE Wake Source */
uint64_t nhla; /* 0x19 - 0x20 - NHLT Address */
diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl
index fcc80d4..b3b3a4f 100644
--- a/src/soc/intel/broadwell/acpi/globalnvs.asl
+++ b/src/soc/intel/broadwell/acpi/globalnvs.asl
@@ -55,7 +55,7 @@
LIDS, 8, // 0x16 - LID State
PWRS, 8, // 0x17 - AC Power State
CMEM, 32, // 0x18 - 0x1b - CBMEM TOC
- CBMC, 32, // 0x1c - 0x1f - Coreboot Memory Console
+ CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console
PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit
GPEI, 64, // 0x28 - 0x2f - GPE wake status bit
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index 202c56a..55d6c8b 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -46,7 +46,7 @@
u8 lids; /* 0x16 - LID State */
u8 pwrs; /* 0x17 - AC Power State */
u32 cmem; /* 0x18 - 0x1b - CBMEM TOC */
- u32 cbmc; /* 0x1c - 0x1f - Coreboot Memory Console */
+ u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */
u8 unused[208];
diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index ab3c63c..d06269f 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -57,7 +57,7 @@
LIDS, 8, // 0x16 - LID State
PWRS, 8, // 0x17 - AC Power State
CMEM, 32, // 0x18 - 0x1b - CBMEM TOC
- CBMC, 32, // 0x1c - 0x1f - Coreboot Memory Console
+ CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console
PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit
GPEI, 64, // 0x28 - 0x2f - GPE wake status bit
DPTE, 8, // 0x30 - Enable DPTF
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 61975c6..ab06948 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -182,7 +182,7 @@
* To disable Heci, the Psf needs to be left unlocked
* by FSP after end of post sequence. Based on the devicetree
* setting, we set the appropriate PsfUnlock policy in Fsp,
- * do the changes and then lock it back in Coreboot
+ * do the changes and then lock it back in coreboot
*
*/
if (config->HeciEnabled == 0)
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 0572413..45dea06 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -226,7 +226,7 @@
if (conf->speed_shift_enable) {
/*
* Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
- is supported or not. Coreboot needs to configure MSR 0x1AA
+ is supported or not. coreboot needs to configure MSR 0x1AA
which is then reflected in the CPUID register.
*/
msr = rdmsr(MSR_MISC_PWR_MGMT);
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index cb3b2c6..f72616f 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -47,7 +47,7 @@
u8 lids; /* 0x16 - LID State */
u8 pwrs; /* 0x17 - AC Power State */
u32 cmem; /* 0x18 - 0x1b - CBMEM TOC */
- u32 cbmc; /* 0x1c - 0x1f - Coreboot Memory Console */
+ u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */
u8 dpte; /* 0x30 - Enable DPTF */
diff --git a/src/soc/samsung/exynos5250/alternate_cbfs.c b/src/soc/samsung/exynos5250/alternate_cbfs.c
index a3431e2..0687d47 100644
--- a/src/soc/samsung/exynos5250/alternate_cbfs.c
+++ b/src/soc/samsung/exynos5250/alternate_cbfs.c
@@ -26,7 +26,7 @@
#include <symbols.h>
/* This allows USB A-A firmware upload from a compatible host in four parts:
- * The first two are the bare BL1 and the Coreboot boot block, which are just
+ * The first two are the bare BL1 and the coreboot boot block, which are just
* written to their respective loading addresses. These transfers are initiated
* by the IROM / BL1, so this code has nothing to do with them.
*
diff --git a/src/soc/samsung/exynos5420/alternate_cbfs.c b/src/soc/samsung/exynos5420/alternate_cbfs.c
index 3a40154..183c371 100644
--- a/src/soc/samsung/exynos5420/alternate_cbfs.c
+++ b/src/soc/samsung/exynos5420/alternate_cbfs.c
@@ -27,7 +27,7 @@
#include <symbols.h>
/* This allows USB A-A firmware upload from a compatible host in four parts:
- * The first two are the bare BL1 and the Coreboot boot block, which are just
+ * The first two are the bare BL1 and the coreboot boot block, which are just
* written to their respective loading addresses. These transfers are initiated
* by the IROM / BL1, so this code has nothing to do with them.
*
diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c
index 7731857..7086da8 100644
--- a/src/soc/samsung/exynos5420/smp.c
+++ b/src/soc/samsung/exynos5420/smp.c
@@ -182,7 +182,7 @@
if (cpu_state & CORE_STATE_RESET) {
/* For Reset, U-Boot jumps to its starting address;
- * on Coreboot, seems ok to ignore for now. */
+ * on coreboot, seems ok to ignore for now. */
}
wait_and_jump(&exynos_cpu_states->hotplug_address);
/* never returns. */
diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc
index 7cdbdec..d6e6296 100644
--- a/src/southbridge/intel/common/firmware/Makefile.inc
+++ b/src/southbridge/intel/common/firmware/Makefile.inc
@@ -41,7 +41,7 @@
add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
printf "\n** WARNING **\n"
- printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
+ printf "coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
printf " IFDFAKE Building a fake Intel Firmware Descriptor\n"
diff --git a/src/vendorcode/amd/cimx/sb700/SBCMN.c b/src/vendorcode/amd/cimx/sb700/SBCMN.c
index 7d5b4f4..ca2ec78 100644
--- a/src/vendorcode/amd/cimx/sb700/SBCMN.c
+++ b/src/vendorcode/amd/cimx/sb700/SBCMN.c
@@ -145,7 +145,7 @@
RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT4, BIT4);
- #if 0 //KZ [083011]-It's used wrong BIOS SIZE for Coreboot.
+ #if 0 //KZ [083011]-It's used wrong BIOS SIZE for coreboot.
//For being compatible with earlier revision, check whether ROM decoding is changed already outside CIMx before
//changing it.
ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG68, AccWidthUint16 | S3_SAVE, &dwTempVar);
diff --git a/src/vendorcode/amd/cimx/sb700/SBPort.c b/src/vendorcode/amd/cimx/sb700/SBPort.c
index 6c5740b..d148481 100644
--- a/src/vendorcode/amd/cimx/sb700/SBPort.c
+++ b/src/vendorcode/amd/cimx/sb700/SBPort.c
@@ -222,7 +222,7 @@
if (dbVar0 > 4) {
dbVar0 = 0;
}
- //KZ [061811]-It's used wrong BIOS SIZE for Coreboot. RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0);
+ //KZ [061811]-It's used wrong BIOS SIZE for coreboot. RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0);
if (pConfig->Spi33Mhz)
//spi reg0c[13:12] to 01h to run spi 33Mhz in system bios
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2
Gerrit-Change-Number: 20029
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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