[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Add config for cpu base clock frequency
Aamir Bohra (Code Review)
gerrit at coreboot.org
Fri Jun 2 16:15:22 CEST 2017
Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/20016
Change subject: soc/intel/skylake: Add config for cpu base clock frequency
......................................................................
soc/intel/skylake: Add config for cpu base clock frequency
Add config for cpu base clock frequency(Mhz) and replace current
refrence from soc/cpu.h with config option.
Change-Id: Idf8e85f7ae6d965fa987a4f5c4905503ee354d69
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/acpi.c
M src/soc/intel/skylake/bootblock/cpu.c
M src/soc/intel/skylake/cpu.c
M src/soc/intel/skylake/include/soc/cpu.h
M src/soc/intel/skylake/tsc_freq.c
6 files changed, 9 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/20016/1
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 80cdde6..067e833 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -323,4 +323,8 @@
int
default 2
+config CPU_BCLK_MHZ
+ int
+ default 100
+
endif
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 77fbb48..f9b39f2 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -410,7 +410,7 @@
/* Max Non-Turbo Ratio */
ratio_max = (msr.lo >> 8) & 0xff;
}
- clock_max = ratio_max * CPU_BCLK;
+ clock_max = ratio_max * CONFIG_CPU_BCLK_MHZ;
/* Calculate CPU TDP in mW */
msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
@@ -474,7 +474,7 @@
/* Calculate power at this ratio */
power = calculate_power(power_max, ratio_max, ratio);
- clock = ratio * CPU_BCLK;
+ clock = ratio * CONFIG_CPU_BCLK_MHZ;
acpigen_write_PSS_package(
clock, /* MHz */
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
index 040e847..23b4b18 100644
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -138,5 +138,5 @@
wrmsr(MSR_IA32_PERF_CTL, perf_ctl);
printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",
- ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
+ ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);
}
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 0572413..95d9ad9 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -320,7 +320,7 @@
wrmsr(IA32_PERF_CTL, perf_ctl);
printk(BIOS_DEBUG, "cpu: frequency set to %d\n",
- ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
+ ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);
}
static void set_energy_perf_bias(u8 policy)
diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h
index 9171172..f6803c9 100644
--- a/src/soc/intel/skylake/include/soc/cpu.h
+++ b/src/soc/intel/skylake/include/soc/cpu.h
@@ -34,9 +34,6 @@
#define CPUID_KABYLAKE_HA0 0x506e8
#define CPUID_KABYLAKE_HB0 0x906e9
-/* CPU bus clock is fixed at 100MHz */
-#define CPU_BCLK 100
-
/* Latency times in units of 1024ns. */
#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x4e
#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x76
diff --git a/src/soc/intel/skylake/tsc_freq.c b/src/soc/intel/skylake/tsc_freq.c
index 9ebe3cb..8a4ff46 100644
--- a/src/soc/intel/skylake/tsc_freq.c
+++ b/src/soc/intel/skylake/tsc_freq.c
@@ -17,7 +17,6 @@
#include <stdint.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/tsc.h>
-#include <soc/cpu.h>
#include <soc/msr.h>
unsigned long tsc_freq_mhz(void)
@@ -25,5 +24,5 @@
msr_t platform_info;
platform_info = rdmsr(MSR_PLATFORM_INFO);
- return CPU_BCLK * ((platform_info.lo >> 8) & 0xff);
+ return CONFIG_CPU_BCLK_MHZ * ((platform_info.lo >> 8) & 0xff);
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Idf8e85f7ae6d965fa987a4f5c4905503ee354d69
Gerrit-Change-Number: 20016
Gerrit-PatchSet: 1
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
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