[coreboot-gerrit] Change in coreboot[master]: intel/common/acpi: Fix ACPI debug log issue with LPSS UART

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20009


Change subject: intel/common/acpi: Fix ACPI debug log issue with LPSS UART
......................................................................

intel/common/acpi: Fix ACPI debug log issue with LPSS UART

This patch fixes ACPI debug print issue reported internally
while using APRT asl method. Potentially some juke characters
gets added into final print buffer.

TEST=Built and boo eve to ensure to be able to get ASL console
log without any corruption.

Change-Id: I0b6af789c0ffc79f7fee4652b4aa6a125b182296
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/common/acpi/acpi_debug.asl
1 file changed, 14 insertions(+), 7 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/20009/1

diff --git a/src/soc/intel/common/acpi/acpi_debug.asl b/src/soc/intel/common/acpi/acpi_debug.asl
index 5b686f2..76805fe 100644
--- a/src/soc/intel/common/acpi/acpi_debug.asl
+++ b/src/soc/intel/common/acpi/acpi_debug.asl
@@ -41,7 +41,8 @@
 	Name(ADBG, Buffer(256) {0})
 
 	If (LEqual(ObjectType(Arg0), 1)) { /* Integer */
-		ToHexString(Arg0, ADBG)
+		ToHexString(Arg0, Local0)
+		Store(Local0, ADBG)
 	} ElseIf (LEqual(ObjectType(Arg0), 2)) { /* String */
 		Store(Arg0, ADBG)
 	} ElseIf (LEqual(ObjectType(Arg0), 3)) { /* Buffer */
@@ -60,12 +61,18 @@
 	OperationRegion (UBAR, SystemMemory, UART_DEBUG_BASE_ADDRESS, 24)
 	Field (UBAR, AnyAcc, NoLock, Preserve)
 	{
-		TDR, 32,	/* Transmit Data Register BAR + 0x000 */
-		IER, 32,	/* Interrupt Enable Register BAR + 0x004 */
-		IIR, 32,	/* Interrupt Identification Register BAR + 0x008 */
-		LCR, 32,	/* Line Control Register BAR + 0x00C */
-		MCR, 32,	/* Modem Control Register BAR + 0x010 */
-		LSR, 32	/* Line Status Register BAR + 0x014 */
+		TDR, 8,	/* Transmit Data Register BAR + 0x000 */
+			, 24,
+		IER, 8,	/* Interrupt Enable Register BAR + 0x004 */
+			, 24,
+		IIR, 8,	/* Interrupt Identification Register BAR + 0x008 */
+			, 24,
+		LCR, 8,	/* Line Control Register BAR + 0x00C */
+			, 24,
+		MCR, 8,	/* Modem Control Register BAR + 0x010 */
+			, 24,
+		LSR, 8,	/* Line Status Register BAR + 0x014 */
+			, 24
 	}
 #else
 	OperationRegion (UBAR, SystemIO, LURT (CONFIG_UART_FOR_CONSOLE), 6)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0b6af789c0ffc79f7fee4652b4aa6a125b182296
Gerrit-Change-Number: 20009
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>