[coreboot-gerrit] Change in coreboot[master]: arch/*: Update Kconfig symbol usage

Martin Roth (Code Review) gerrit at coreboot.org
Thu Jun 1 19:44:24 CEST 2017 

Martin Roth has uploaded a new change for review. ( https://review.coreboot.org/20005 )

Change subject: arch/*: Update Kconfig symbol usage
......................................................................

arch/*: Update Kconfig symbol usage

- Update all symbols to use IS_ENABLED()
- Update non-romcc usage to use 'if' instead of '#if' where it
makes sense.

Change-Id: I5a84414d2d1631e35ac91efb67a0d4c1f673bf85
Signed-off-by: Martin Roth <martinroth at google.com>
---
M src/arch/arm/armv7/mmu.c
M src/arch/arm/include/armv7/arch/cache.h
M src/arch/arm/include/armv7/arch/cpu.h
M src/arch/mips/bootblock_simple.c
M src/arch/power8/include/arch/cpu.h
M src/arch/riscv/include/arch/cpu.h
M src/arch/x86/acpi_s3.c
M src/arch/x86/bootblock_normal.c
M src/arch/x86/bootblock_simple.c
M src/arch/x86/c_start.S
M src/arch/x86/exception.c
M src/arch/x86/ioapic.c
M src/arch/x86/pirq_routing.c
M src/arch/x86/romcc_console.c
M src/arch/x86/smbios.c
15 files changed, 60 insertions(+), 62 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/20005/1

diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
index 4123bb4..6b383cc 100644
--- a/src/arch/arm/armv7/mmu.c
+++ b/src/arch/arm/armv7/mmu.c
@@ -39,7 +39,7 @@
 #include <arch/cache.h>
 #include <arch/io.h>
 
-#if CONFIG_ARM_LPAE
+#if IS_ENABLED(CONFIG_ARM_LPAE)
 /* See B3.6.2 of ARMv7 Architecture Reference Manual */
 /* TODO: Utilize the contiguous hint flag */
 #define ATTR_BLOCK (\
diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h
index 1e64777..dd271c5 100644
--- a/src/arch/arm/include/armv7/arch/cache.h
+++ b/src/arch/arm/include/armv7/arch/cache.h
@@ -134,12 +134,11 @@
 /* write translation table base register 0 (TTBR0) */
 static inline void write_ttbr0(uint32_t val)
 {
-#if CONFIG_ARM_LPAE
-	asm volatile ("mcrr p15, 0, %[val], %[zero], c2" : :
+	if (IS_ENABLED(CONFIG_ARM_LPAE))
+		asm volatile ("mcrr p15, 0, %[val], %[zero], c2" : :
 			[val] "r" (val), [zero] "r" (0));
-#else
-	asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (val) : "memory");
-#endif
+	else
+		asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (val) : "memory");
 }
 
 /* read translation table base control register (TTBCR) */
diff --git a/src/arch/arm/include/armv7/arch/cpu.h b/src/arch/arm/include/armv7/arch/cpu.h
index d70622f..dddf712 100644
--- a/src/arch/arm/include/armv7/arch/cpu.h
+++ b/src/arch/arm/include/armv7/arch/cpu.h
@@ -33,7 +33,7 @@
 struct cpu_info {
 	device_t cpu;
 	unsigned long index;
-#if CONFIG_COOP_MULTITASKING
+#if IS_ENABLED(CONFIG_COOP_MULTITASKING)
 	struct thread *thread;
 #endif
 };
diff --git a/src/arch/mips/bootblock_simple.c b/src/arch/mips/bootblock_simple.c
index c3bd82d..46c961e 100644
--- a/src/arch/mips/bootblock_simple.c
+++ b/src/arch/mips/bootblock_simple.c
@@ -26,7 +26,7 @@
 	/* Mainboard basic init */
 	bootblock_mainboard_init();
 
-#if CONFIG_BOOTBLOCK_CONSOLE
+#if IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)
 	console_init();
 #endif
 
diff --git a/src/arch/power8/include/arch/cpu.h b/src/arch/power8/include/arch/cpu.h
index 45ebc14..9acc2a8 100644
--- a/src/arch/power8/include/arch/cpu.h
+++ b/src/arch/power8/include/arch/cpu.h
@@ -31,7 +31,7 @@
 struct cpu_info {
 	device_t cpu;
 	unsigned long index;
-#if CONFIG_COOP_MULTITASKING
+#if IS_ENABLED(CONFIG_COOP_MULTITASKING)
 	struct thread *thread;
 #endif
 };
diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h
index bc7b196..ae5cbda 100644
--- a/src/arch/riscv/include/arch/cpu.h
+++ b/src/arch/riscv/include/arch/cpu.h
@@ -31,7 +31,7 @@
 struct cpu_info {
 	device_t cpu;
 	unsigned long index;
-#if CONFIG_COOP_MULTITASKING
+#if IS_ENABLED(CONFIG_COOP_MULTITASKING)
 	struct thread *thread;
 #endif
 };
diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c
index 61955f5..d81f076 100644
--- a/src/arch/x86/acpi_s3.c
+++ b/src/arch/x86/acpi_s3.c
@@ -247,7 +247,7 @@
 
 void acpi_resume(void *wake_vec)
 {
-#if CONFIG_HAVE_SMI_HANDLER
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
 	u32 *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS_PTR);
 
 	/* Restore GNVS pointer in SMM if found */
diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c
index caffb91..4230469 100644
--- a/src/arch/x86/bootblock_normal.c
+++ b/src/arch/x86/bootblock_normal.c
@@ -32,7 +32,7 @@
 	if (boot_cpu()) {
 		bootblock_mainboard_init();
 
-#if CONFIG_USE_OPTION_TABLE
+#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
 		sanitize_cmos();
 #endif
 		boot_mode = do_normal_boot();
diff --git a/src/arch/x86/bootblock_simple.c b/src/arch/x86/bootblock_simple.c
index 5df279c..52c45be 100644
--- a/src/arch/x86/bootblock_simple.c
+++ b/src/arch/x86/bootblock_simple.c
@@ -20,15 +20,15 @@
 	if (boot_cpu()) {
 		bootblock_mainboard_init();
 
-#if CONFIG_USE_OPTION_TABLE
+#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
 		sanitize_cmos();
 #endif
-#if CONFIG_CMOS_POST
+#if IS_ENABLED(CONFIG_CMOS_POST)
 		cmos_post_init();
 #endif
 	}
 
-#if CONFIG_VBOOT_SEPARATE_VERSTAGE
+#if IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE)
 	const char *target1 = "fallback/verstage";
 #else
 	const char *target1 = "fallback/romstage";
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 9ad2698..97e2b5a 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -23,7 +23,7 @@
 _stack:
 .space CONFIG_MAX_CPUS*CONFIG_STACK_SIZE
 _estack:
-#if CONFIG_COOP_MULTITASKING
+#if IS_ENABLED(CONFIG_COOP_MULTITASKING)
 .global thread_stacks
 thread_stacks:
 .space CONFIG_STACK_SIZE*CONFIG_NUM_THREADS
@@ -73,7 +73,7 @@
 	/* set new stack */
 	movl	$_estack, %esp
 
-#if CONFIG_COOP_MULTITASKING
+#if IS_ENABLED(CONFIG_COOP_MULTITASKING)
 	/* Push the thread pointer. */
 	push	$0
 #endif
@@ -112,7 +112,7 @@
 
 	andl	$0xFFFFFFF0, %esp
 
-#if CONFIG_GDB_WAIT
+#if IS_ENABLED(CONFIG_GDB_WAIT)
 	call gdb_hw_init
 	call gdb_stub_breakpoint
 #endif
@@ -294,7 +294,7 @@
 
 	iret
 
-#if CONFIG_GDB_WAIT
+#if IS_ENABLED(CONFIG_GDB_WAIT)
 
 	.globl gdb_stub_breakpoint
 gdb_stub_breakpoint:
diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c
index 9121738..36697c6 100644
--- a/src/arch/x86/exception.c
+++ b/src/arch/x86/exception.c
@@ -15,7 +15,7 @@
 #include <console/streams.h>
 #include <string.h>
 
-#if CONFIG_GDB_STUB
+#if IS_ENABLED(CONFIG_GDB_STUB)
 
 /* BUFMAX defines the maximum number of characters in inbound/outbound buffers.
  * At least NUM_REGBYTES*2 are needed for register packets
@@ -387,7 +387,7 @@
 
 void x86_exception(struct eregs *info)
 {
-#if CONFIG_GDB_STUB
+#if IS_ENABLED(CONFIG_GDB_STUB)
 	int signo;
 	memcpy(gdb_stub_registers, info, 8*sizeof(uint32_t));
 	gdb_stub_registers[PC] = info->eip;
diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c
index 25fc84c..12ffde0 100644
--- a/src/arch/x86/ioapic.c
+++ b/src/arch/x86/ioapic.c
@@ -103,19 +103,20 @@
 
 	ioapic_interrupts = ioapic_interrupt_count(ioapic_base);
 
-#if CONFIG_IOAPIC_INTERRUPTS_ON_FSB
-	/*
-	 * For the Pentium 4 and above APICs deliver their interrupts
-	 * on the front side bus, enable that.
-	 */
-	printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n");
-	io_apic_write(ioapic_base, 0x03,
-		      io_apic_read(ioapic_base, 0x03) | (1 << 0));
-#endif
-#if CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
-	printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n");
-	io_apic_write(ioapic_base, 0x03, 0);
-#endif
+	if (IS_ENABLED(CONFIG_IOAPIC_INTERRUPTS_ON_FSB)) {
+		/*
+		 * For the Pentium 4 and above APICs deliver their interrupts
+		 * on the front side bus, enable that.
+		 */
+		printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n");
+		io_apic_write(ioapic_base, 0x03,
+			      io_apic_read(ioapic_base, 0x03) | (1 << 0));
+	}
+	if (IS_ENABLED(CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS)) {
+		printk(BIOS_DEBUG,
+			"IOAPIC: Enabling interrupts on APIC serial bus\n");
+		io_apic_write(ioapic_base, 0x03, 0);
+	}
 
 	/* Enable Virtual Wire Mode. */
 	low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c
index 405dad0..2ca7e9e 100644
--- a/src/arch/x86/pirq_routing.c
+++ b/src/arch/x86/pirq_routing.c
@@ -19,7 +19,7 @@
 #include <string.h>
 #include <device/pci.h>
 
-#if CONFIG_DEBUG_PIRQ
+#if IS_ENABLED(CONFIG_DEBUG_PIRQ)
 static void check_pirq_routing_table(struct irq_routing_table *rt)
 {
 	uint8_t *addr = (uint8_t *)rt;
@@ -99,7 +99,7 @@
 }
 #endif
 
-#if CONFIG_PIRQ_ROUTE
+#if IS_ENABLED(CONFIG_PIRQ_ROUTE)
 static u8 pirq_get_next_free_irq(u8 *pirq, u16 bitmap)
 {
 	int i, link;
@@ -198,11 +198,10 @@
 		addr);
 	memcpy((void *)addr, routing_table, routing_table->size);
 	printk(BIOS_INFO, "done.\n");
-#if CONFIG_DEBUG_PIRQ
-	verify_copy_pirq_routing_table(addr, routing_table);
-#endif
-#if CONFIG_PIRQ_ROUTE
-	pirq_route_irqs(addr);
-#endif
+	if (IS_ENABLED(CONFIG_DEBUG_PIRQ))
+		verify_copy_pirq_routing_table(addr, routing_table);
+	if IS_ENABLED(CONFIG_PIRQ_ROUTE)
+		pirq_route_irqs(addr);
+
 	return addr + routing_table->size;
 }
diff --git a/src/arch/x86/romcc_console.c b/src/arch/x86/romcc_console.c
index fa706d0..f5c8b9b 100644
--- a/src/arch/x86/romcc_console.c
+++ b/src/arch/x86/romcc_console.c
@@ -19,40 +19,40 @@
 #include <commonlib/loglevel.h>
 
 /* Include the sources. */
-#if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO
+#if IS_ENABLED(CONFIG_CONSOLE_SERIAL) && IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)
 #include "drivers/uart/util.c"
 #include "drivers/uart/uart8250io.c"
 #endif
-#if CONFIG_CONSOLE_NE2K
+#if IS_ENABLED(CONFIG_CONSOLE_NE2K)
 #include "drivers/net/ne2k.c"
 #endif
 
 void console_hw_init(void)
 {
-#if CONFIG_CONSOLE_SERIAL
+#if IS_ENABLED(CONFIG_CONSOLE_SERIAL)
 	uart_init(CONFIG_UART_FOR_CONSOLE);
 #endif
-#if CONFIG_CONSOLE_NE2K
+#if IS_ENABLED(CONFIG_CONSOLE_NE2K)
 	ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT);
 #endif
 }
 
 void console_tx_byte(unsigned char byte)
 {
-#if CONFIG_CONSOLE_SERIAL
+#if IS_ENABLED(CONFIG_CONSOLE_SERIAL)
 	uart_tx_byte(CONFIG_UART_FOR_CONSOLE, byte);
 #endif
-#if CONFIG_CONSOLE_NE2K
+#if IS_ENABLED(CONFIG_CONSOLE_NE2K)
 	ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT);
 #endif
 }
 
 void console_tx_flush(void)
 {
-#if CONFIG_CONSOLE_SERIAL
+#if IS_ENABLED(CONFIG_CONSOLE_SERIAL)
 	uart_tx_flush(CONFIG_UART_FOR_CONSOLE);
 #endif
-#if CONFIG_CONSOLE_NE2K
+#if IS_ENABLED(CONFIG_CONSOLE_NE2K)
 	ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT);
 #endif
 }
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index 0909900..6a92e3f 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -29,7 +29,7 @@
 #include <memory_info.h>
 #include <spd.h>
 #include <cbmem.h>
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
 #include <vendorcode/google/chromeos/gnvs.h>
 #endif
 
@@ -311,22 +311,22 @@
 	t->system_bios_major_release = 4;
 	t->bios_characteristics =
 		BIOS_CHARACTERISTICS_PCI_SUPPORTED |
-#if CONFIG_CARDBUS_PLUGIN_SUPPORT
-		BIOS_CHARACTERISTICS_PC_CARD |
-#endif
 		BIOS_CHARACTERISTICS_SELECTABLE_BOOT |
 		BIOS_CHARACTERISTICS_UPGRADEABLE;
 
-#if CONFIG_HAVE_ACPI_TABLES
-	t->bios_characteristics_ext1 = BIOS_EXT1_CHARACTERISTICS_ACPI;
-#endif
+	if IS_ENABLED(CONFIG_CARDBUS_PLUGIN_SUPPORT)
+		t->bios_characteristics |= BIOS_CHARACTERISTICS_PC_CARD;
+
+	if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+		t->bios_characteristics_ext1 = BIOS_EXT1_CHARACTERISTICS_ACPI;
+
 	t->bios_characteristics_ext2 = BIOS_EXT2_CHARACTERISTICS_TARGET;
 	len = t->length + smbios_string_table_len(t->eos);
 	*current += len;
 	return len;
 }
 
-#if !CONFIG_SMBIOS_PROVIDED_BY_MOBO
+#if !IS_ENABLED(CONFIG_SMBIOS_PROVIDED_BY_MOBO)
 
 const char *__attribute__((weak)) smbios_mainboard_serial_number(void)
 {
@@ -625,10 +625,9 @@
 		handle++));
 	update_max(len, max_struct_size, smbios_write_type11(&current,
 		&handle));
-#if CONFIG_ELOG
-	update_max(len, max_struct_size, elog_smbios_write_type15(&current,
-		handle++));
-#endif
+	if (IS_ENABLED(CONFIG_ELOG))
+		update_max(len, max_struct_size,
+			elog_smbios_write_type15(&current,handle++));
 	update_max(len, max_struct_size, smbios_write_type17(&current,
 		&handle));
 	update_max(len, max_struct_size, smbios_write_type32(&current,

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I5a84414d2d1631e35ac91efb67a0d4c1f673bf85
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Martin Roth <martinroth at google.com>

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