[coreboot-gerrit] Change in coreboot[master]: mainboard/hp: Add HP Elitebook 8460p
Iru Cai (Code Review)
gerrit at coreboot.org
Wed Jul 26 08:52:38 CEST 2017
Iru Cai has uploaded this change for review. ( https://review.coreboot.org/20780
Change subject: mainboard/hp: Add HP Elitebook 8460p
......................................................................
mainboard/hp: Add HP Elitebook 8460p
The code is based on autoport. I'm using a machine with discrete GPU,
and gfx.* in devicetree.cb is from 2760p.
Tested:
- CPU and memory: i5-2540M, 4G+0
- Linux (SeaBIOS payload, with ATOM BIOS extracted from vendor UEFI firmware)
- USB ports
Change-Id: Id6fb883785f6bca43e4299fd2e73ef263dbad768
Signed-off-by: Iru Cai <mytbk920423 at gmail.com>
---
A src/mainboard/hp/8460p/Kconfig
A src/mainboard/hp/8460p/Kconfig.name
A src/mainboard/hp/8460p/Makefile.inc
A src/mainboard/hp/8460p/board_info.txt
A src/mainboard/hp/8460p/devicetree.cb
A src/mainboard/hp/8460p/gpio.c
A src/mainboard/hp/8460p/hda_verb.c
A src/mainboard/hp/8460p/romstage.c
8 files changed, 549 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/20780/1
diff --git a/src/mainboard/hp/8460p/Kconfig b/src/mainboard/hp/8460p/Kconfig
new file mode 100644
index 0000000..f66e39d
--- /dev/null
+++ b/src/mainboard/hp/8460p/Kconfig
@@ -0,0 +1,40 @@
+if BOARD_HP_8460P
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select HP_ELITEBOOK_SNB_IVB
+ select BOARD_ROMSIZE_KB_8192
+ select CPU_INTEL_SOCKET_RPGA989
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SOUTHBRIDGE_INTEL_BD82X6X
+ select SUPERIO_SMSC_LPC47N217
+
+config DEVICETREE
+ string
+ default ../8460p/devicetree.cb
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "EliteBook 8460p"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0116.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0116"
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x161c
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x103c
+
+config USBDEBUG_HCD_INDEX
+ int
+ default 1
+
+endif
diff --git a/src/mainboard/hp/8460p/Kconfig.name b/src/mainboard/hp/8460p/Kconfig.name
new file mode 100644
index 0000000..94f2fe9
--- /dev/null
+++ b/src/mainboard/hp/8460p/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_HP_8460P
+ bool "EliteBook 8460p"
diff --git a/src/mainboard/hp/8460p/Makefile.inc b/src/mainboard/hp/8460p/Makefile.inc
new file mode 100644
index 0000000..8bb3cd6
--- /dev/null
+++ b/src/mainboard/hp/8460p/Makefile.inc
@@ -0,0 +1,4 @@
+romstage-y += romstage.c
+romstage-y += gpio.c
+
+ramstage-y += hda_verb.c
diff --git a/src/mainboard/hp/8460p/board_info.txt b/src/mainboard/hp/8460p/board_info.txt
new file mode 100644
index 0000000..024040b
--- /dev/null
+++ b/src/mainboard/hp/8460p/board_info.txt
@@ -0,0 +1,7 @@
+Category: laptop
+Board URL: https://support.hp.com/us-en/product/HP-EliteBook-8460p-Notebook-PC/5056942
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n
+Release year: 2011
diff --git a/src/mainboard/hp/8460p/devicetree.cb b/src/mainboard/hp/8460p/devicetree.cb
new file mode 100644
index 0000000..2187848
--- /dev/null
+++ b/src/mainboard/hp/8460p/devicetree.cb
@@ -0,0 +1,155 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2017 Iru Cai <mytbk920423 at gmail.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+ register "gfx.link_frequency_270_mhz" = "1"
+ register "gfx.ndid" = "3"
+ register "gfx.use_spread_spectrum_clock" = "1"
+ register "gpu_cpu_backlight" = "0x00000129"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2000"
+ register "gpu_panel_power_backlight_on_delay" = "2000"
+ register "gpu_panel_power_cycle_delay" = "5"
+ register "gpu_panel_power_down_delay" = "230"
+ register "gpu_panel_power_up_delay" = "300"
+ register "gpu_pch_backlight" = "0x02880288"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0x0 on
+ end
+ end
+ chip cpu/intel/model_206ax # FIXME: check all registers
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0xacac off
+ end
+ end
+ end
+ device domain 0x0 on
+ device pci 00.0 on # Host bridge
+ subsystemid 0x103c 0x161c
+ end
+ device pci 01.0 on # PCIe Bridge for discrete graphics
+ end
+ device pci 02.0 on # Internal graphics
+ subsystemid 0x103c 0x161c
+ end
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "docking_supported" = "0"
+ register "gen1_dec" = "0x007c0201"
+ register "gen2_dec" = "0x000c0101"
+ register "gen3_dec" = "0x00fcfe01"
+ register "gen4_dec" = "0x000402e9"
+ register "gpi6_routing" = "2"
+ register "p_cnt_throttling_supported" = "1"
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x3b"
+
+ register "spi_uvscc" = "0x2005"
+ register "spi_lvscc" = "0"
+
+ device pci 16.0 on # Management Engine Interface 1
+ subsystemid 0x103c 0x161c
+ end
+ device pci 16.1 off # Management Engine Interface 2
+ end
+ device pci 16.2 off # Management Engine IDE-R
+ end
+ device pci 16.3 on # Management Engine KT
+ subsystemid 0x103c 0x161c
+ end
+ device pci 19.0 on # Intel Gigabit Ethernet
+ subsystemid 0x103c 0x161c
+ end
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x103c 0x161c
+ end
+ device pci 1b.0 on # High Definition Audio Audio controller
+ subsystemid 0x103c 0x161c
+ end
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x103c 0x161c
+ end
+ device pci 1c.1 on # PCIe Port #2
+ subsystemid 0x103c 0x161c
+ end
+ device pci 1c.2 on # PCIe Port #3
+ subsystemid 0x103c 0x161c
+ end
+ device pci 1c.3 on # PCIe Port #4
+ subsystemid 0x103c 0x161c
+ end
+ device pci 1c.4 off # PCIe Port #5
+ end
+ device pci 1c.5 off # PCIe Port #6
+ end
+ device pci 1c.6 off # PCIe Port #7
+ end
+ device pci 1c.7 on # PCIe Port #8
+ subsystemid 0x103c 0x161c
+ end
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x103c 0x161c
+ end
+ device pci 1e.0 off # PCI bridge
+ end
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ subsystemid 0x103c 0x161c
+ chip ec/hp/kbc1126
+ register "ec_data_port" = "0x60"
+ register "ec_cmd_port" = "0x64"
+ register "ec_ctrl_reg" = "0xca"
+ register "ec_fan_ctrl_value" = "0x6b"
+ device pnp ff.1 off end
+ end # kbc1126
+ chip superio/smsc/lpc47n217
+ device pnp 4e.3 off # Parallel
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 4e.4 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 4e.5 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ end #chip superio/smsc/lpc47n217
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x103c 0x161c
+ end
+ device pci 1f.3 off # SMBus
+ end
+ device pci 1f.5 off # SATA Controller 2
+ end
+ device pci 1f.6 off # Thermal
+ end
+ end
+ end
+end
diff --git a/src/mainboard/hp/8460p/gpio.c b/src/mainboard/hp/8460p/gpio.c
new file mode 100644
index 0000000..0a508cbc
--- /dev/null
+++ b/src/mainboard/hp/8460p/gpio.c
@@ -0,0 +1,240 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+const static struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_NATIVE,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+const static struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_OUTPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_OUTPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+};
+
+const static struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio0 = GPIO_LEVEL_LOW,
+ .gpio11 = GPIO_LEVEL_LOW,
+ .gpio17 = GPIO_LEVEL_HIGH,
+ .gpio22 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_HIGH,
+ .gpio27 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio29 = GPIO_LEVEL_HIGH,
+};
+
+const static struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio24 = GPIO_RESET_RSMRST,
+ .gpio30 = GPIO_RESET_RSMRST,
+};
+
+const static struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio3 = GPIO_INVERT,
+ .gpio6 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+ .gpio10 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+const static struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+const static struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_GPIO,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_GPIO,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+const static struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_OUTPUT,
+ .gpio37 = GPIO_DIR_OUTPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio44 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio55 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_OUTPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+ .gpio61 = GPIO_DIR_OUTPUT,
+};
+
+const static struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio33 = GPIO_LEVEL_LOW,
+ .gpio35 = GPIO_LEVEL_LOW,
+ .gpio36 = GPIO_LEVEL_LOW,
+ .gpio37 = GPIO_LEVEL_LOW,
+ .gpio49 = GPIO_LEVEL_LOW,
+ .gpio53 = GPIO_LEVEL_HIGH,
+ .gpio57 = GPIO_LEVEL_HIGH,
+ .gpio60 = GPIO_LEVEL_HIGH,
+ .gpio61 = GPIO_LEVEL_HIGH,
+};
+
+const static struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+const static struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_GPIO,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+const static struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_OUTPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_OUTPUT,
+ .gpio71 = GPIO_DIR_OUTPUT,
+ .gpio72 = GPIO_DIR_OUTPUT,
+ .gpio73 = GPIO_DIR_OUTPUT,
+ .gpio74 = GPIO_DIR_OUTPUT,
+};
+
+const static struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio68 = GPIO_LEVEL_HIGH,
+ .gpio70 = GPIO_LEVEL_HIGH,
+ .gpio71 = GPIO_LEVEL_HIGH,
+ .gpio72 = GPIO_LEVEL_LOW,
+ .gpio73 = GPIO_LEVEL_HIGH,
+ .gpio74 = GPIO_LEVEL_HIGH,
+};
+
+const static struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/hp/8460p/hda_verb.c b/src/mainboard/hp/8460p/hda_verb.c
new file mode 100644
index 0000000..8436707
--- /dev/null
+++ b/src/mainboard/hp/8460p/hda_verb.c
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d7605, /* Codec Vendor / Device ID: IDT */
+ 0x103c3588, /* Subsystem ID */
+
+ 0x0000000b, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x0, 0x103c3588),
+
+ /* NID 0x0a. */
+ AZALIA_PIN_CFG(0x0, 0x0a, 0x40f000f0),
+
+ /* NID 0x0b. */
+ AZALIA_PIN_CFG(0x0, 0x0b, 0x0421401f),
+
+ /* NID 0x0c. */
+ AZALIA_PIN_CFG(0x0, 0x0c, 0x04a11020),
+
+ /* NID 0x0d. */
+ AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110),
+
+ /* NID 0x0e. */
+ AZALIA_PIN_CFG(0x0, 0x0e, 0x40f000f0),
+
+ /* NID 0x0f. */
+ AZALIA_PIN_CFG(0x0, 0x0f, 0x40f000f0),
+
+ /* NID 0x10. */
+ AZALIA_PIN_CFG(0x0, 0x10, 0x40f000f0),
+
+ /* NID 0x11. */
+ AZALIA_PIN_CFG(0x0, 0x11, 0x90a60130),
+
+ /* NID 0x1f. */
+ AZALIA_PIN_CFG(0x0, 0x1f, 0x40f000f0),
+
+ /* NID 0x20. */
+ AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0),
+ 0x11c11040, /* Codec Vendor / Device ID: LSI */
+ 0x103c3066, /* Subsystem ID */
+
+ 0x00000001, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x1, 0x103c3066),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/romstage.c
new file mode 100644
index 0000000..c6d4986
--- /dev/null
+++ b/src/mainboard/hp/8460p/romstage.c
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Iru Cai <mytbk920423 at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 0, 0 },
+ { 0, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 0, 2 },
+ { 1, 0, 2 },
+ { 0, 0, 3 },
+ { 1, 0, 3 },
+ { 1, 1, 4 },
+ { 1, 1, 4 },
+ { 1, 0, 5 },
+ { 1, 0, 5 },
+ { 1, 0, 6 },
+ { 1, 0, 6 },
+};
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id6fb883785f6bca43e4299fd2e73ef263dbad768
Gerrit-Change-Number: 20780
Gerrit-PatchSet: 1
Gerrit-Owner: Iru Cai <mytbk920423 at gmail.com>
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