[coreboot-gerrit] Change in coreboot[master]: src/northbridge: Add guards on all header files

[Martin Roth (Code Review)]

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20747


Change subject: src/northbridge: Add guards on all header files
......................................................................

src/northbridge: Add guards on all header files

Change-Id: I93b939478615f22f2c078b1efb7999ad4f3a4c28
Signed-off-by: Martin Roth <martinroth at google.com>
---
M src/northbridge/amd/amdfam10/ht_config.h
M src/northbridge/via/cn700/cn700.h
M src/northbridge/via/cx700/registers.h
M src/northbridge/via/vx900/chip.h
4 files changed, 20 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/20747/1

diff --git a/src/northbridge/amd/amdfam10/ht_config.h b/src/northbridge/amd/amdfam10/ht_config.h
index bcfcf44..75626fa 100644
--- a/src/northbridge/amd/amdfam10/ht_config.h
+++ b/src/northbridge/amd/amdfam10/ht_config.h
@@ -13,6 +13,9 @@
  * GNU General Public License for more details.
  */
 
+#ifndef __AMDFAM10_HT_CONFIG_H__
+#define __AMDFAM10_HT_CONFIG_H__
+
 typedef struct amdfam10_sysconf_t sys_info_conf_t;
 
 /* FIXME */
@@ -47,3 +50,5 @@
 				u32 io_min, u32 io_max);
 
 void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes);
+
+#endif
diff --git a/src/northbridge/via/cn700/cn700.h b/src/northbridge/via/cn700/cn700.h
index 453b7f5..a5e8c1c 100644
--- a/src/northbridge/via/cn700/cn700.h
+++ b/src/northbridge/via/cn700/cn700.h
@@ -14,6 +14,9 @@
  * GNU General Public License for more details.
  */
 
+#ifndef __VIA_CN700_H__
+#define __VIA_CN700_H__
+
 /* VGA stuff */
 #define SR_INDEX		0x3c4
 #define SR_DATA			0x3c5
@@ -43,3 +46,5 @@
 #define RAM_COMMAND_PRECHARGE	0x2
 #define RAM_COMMAND_MRS		0x3
 #define RAM_COMMAND_CBR		0x4
+
+#endif
diff --git a/src/northbridge/via/cx700/registers.h b/src/northbridge/via/cx700/registers.h
index 02ec02a..f8b475b 100644
--- a/src/northbridge/via/cx700/registers.h
+++ b/src/northbridge/via/cx700/registers.h
@@ -13,6 +13,9 @@
  * GNU General Public License for more details.
  */
 
+#ifndef __CX700_REGISTERS_H__
+#define __CX700_REGISTERS_H__
+
 /* CX700 has 48 bytes of scratch registers in D0F4 starting at Reg. 0xd0 */
 #define	SCRATCH_REG_BASE		0xd0
 #define	SCRATCH_RANK_0			0xd0
@@ -38,3 +41,5 @@
 #define DDRII_333	0x2
 #define DDRII_266	0x1
 #define DDRII_200	0x0
+
+#endif
diff --git a/src/northbridge/via/vx900/chip.h b/src/northbridge/via/vx900/chip.h
index 3ba7583..0a2857d 100644
--- a/src/northbridge/via/vx900/chip.h
+++ b/src/northbridge/via/vx900/chip.h
@@ -14,6 +14,9 @@
  * GNU General Public License for more details.
  */
 
+#ifndef __VX900_CHIP_H__
+#define __VX900_CHIP_H__
+
 struct northbridge_via_vx900_config {
 	/**
 	 * \brief PCIe Lane[3:0] Function Select
@@ -47,3 +50,5 @@
 	 */
 	char ext_int_route_to_pirq;
 };
+
+#endif

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I93b939478615f22f2c078b1efb7999ad4f3a4c28
Gerrit-Change-Number: 20747
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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