[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Add max SPI transaction timeout as 5 sec

[Barnali Sarkar (Code Review)]

Barnali Sarkar has uploaded this change for review. ( https://review.coreboot.org/20738


Change subject: soc/intel/common/block: Add max SPI transaction timeout as 5 sec
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soc/intel/common/block: Add max SPI transaction timeout as 5 sec

Earlier 15ms Timeout was kept for SPI transactions which was not
enough for SPI Erase transactions.

Increased the max timeout time to 5 secs which was present in SKL
before common code.
This increase in timeout wont disturb other SPI transactions like
Read, Write or Read Status, since, for those it will come out of
the loop once FDONE bit or FCERR bit is set.

BUG=b:63959637
BRANCH=none
TEST=Built and boot poppy and all SPI transactions suceeeds.

Change-Id: I1c015d80b33677de11755fb2097373631d1fa8c4
Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
---
M src/soc/intel/common/block/fast_spi/fast_spi_def.h
1 file changed, 1 insertion(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/20738/1

diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h
index 1262e6a..e2edcc0 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h
+++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h
@@ -150,7 +150,7 @@
 /* Programmable values of Bit0(SSMS) of Set STRAP MSG Control (0xF4) Register*/
 #define SPIBAR_RESET_CTRL_SSMC		1 /* Set_Strap Mux Select(SSMS) Bit=1*/
 
-#define SPIBAR_HWSEQ_XFER_TIMEOUT	15 /* 15ms*/
+#define SPIBAR_HWSEQ_XFER_TIMEOUT	5000 /* max 5 secs*/
 
 void *fast_spi_get_bar(void);
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1c015d80b33677de11755fb2097373631d1fa8c4
Gerrit-Change-Number: 20738
Gerrit-PatchSet: 1
Gerrit-Owner: Barnali Sarkar <barnali.sarkar at intel.com>
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