[coreboot-gerrit] Change in coreboot[master]: nb/amd/lx: correctly check cache shadow bits

Martin Roth (Code Review) gerrit at coreboot.org
Sun Jul 23 01:35:05 CEST 2017


Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20697


Change subject: nb/amd/lx: correctly check cache shadow bits
......................................................................

nb/amd/lx: correctly check cache shadow bits

Fixes error found by GCC 7.1:
src/northbridge/amd/lx/northbridgeinit.c:519:24: error: '<<' in
boolean context, did you mean '<' ?

Change-Id: Ic554797edd211209698759c627aaadb1594034e5
Signed-off-by: Martin Roth <martinroth at google.com>
---
M src/northbridge/amd/lx/northbridgeinit.c
1 file changed, 4 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/20697/1

diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c
index f588ead..5d97c08 100644
--- a/src/northbridge/amd/lx/northbridgeinit.c
+++ b/src/northbridge/amd/lx/northbridgeinit.c
@@ -488,7 +488,7 @@
 	for (bit = 8; (bit > 4); bit--) {
 		msr.hi <<= 8;
 		msr.hi |= 1;	// cache disable PCI/Shadow memory
-		if (shadowByte && (1 << bit))
+		if (shadowByte & (1 << bit))
 			msr.hi |= 0x20;	// write serialize PCI memory
 	}
 
@@ -496,7 +496,7 @@
 	for (; bit; bit--) {
 		msr.lo <<= 8;
 		msr.lo |= 1;	// cache disable PCI/Shadow memory
-		if (shadowByte && (1 << bit))
+		if (shadowByte & (1 << bit))
 			msr.lo |= 0x20;	// write serialize PCI memory
 	}
 
@@ -508,7 +508,7 @@
 	for (bit = 8; (bit > 4); bit--) {
 		msr.hi <<= 8;
 		msr.hi |= 1;	// cache disable PCI/Shadow memory
-		if (shadowByte && (1 << bit))
+		if (shadowByte & (1 << bit))
 			msr.hi |= 0x20;	// write serialize PCI memory
 	}
 
@@ -516,7 +516,7 @@
 	for (; bit; bit--) {
 		msr.lo <<= 8;
 		msr.lo |= 1;	// cache disable PCI/Shadow memory
-		if (shadowByte && (1 << bit))
+		if (shadowByte & (1 << bit))
 			msr.lo |= 0x20;	// write serialize PCI memory
 	}
 

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic554797edd211209698759c627aaadb1594034e5
Gerrit-Change-Number: 20697
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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