[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add postcar stage support
Martin Roth (Code Review)
gerrit at coreboot.org
Fri Jul 21 19:49:55 CEST 2017
Hello Lijian Zhao,
I'd like you to do a code review. Please visit
https://review.coreboot.org/20688
to review the following change.
Change subject: soc/intel/cannonlake: Add postcar stage support
......................................................................
soc/intel/cannonlake: Add postcar stage support
Initialize postcar frame once finish FSP memoryinit
This patch was merged too early and reverted.
Originally reviewed on https://review.coreboot.org/#/c/20534
Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/drivers/intel/fsp2_0/Makefile.inc
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/cannonlake/romstage/romstage.c
M src/soc/intel/cannonlake/uart.c
5 files changed, 38 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/20688/1
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
index cdf6146..d5709ad 100644
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -43,6 +43,7 @@
postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c
postcar-$(CONFIG_FSP_CAR) += util.c
postcar-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c
+postcar-y += hand_off_block.c
CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 1c0f1bf..483bb67 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -23,6 +23,8 @@
select HAVE_INTEL_FIRMWARE
select INTEL_CAR_NEM_ENHANCED
select PLATFORM_USES_FSP2_0
+ select POSTCAR_CONSOLE
+ select POSTCAR_STAGE
select RELOCATABLE_RAMSTAGE
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_BLOCK_SA
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 1557b2e..2549e4c 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -5,20 +5,23 @@
subdirs-y += ../../../cpu/x86/mtrr
subdirs-y += ../../../cpu/x86/tsc
-bootblock-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
bootblock-y += bootblock/bootblock.c
bootblock-y += bootblock/cpu.c
bootblock-y += bootblock/pch.c
bootblock-y += bootblock/report_platform.c
bootblock-y += gpio.c
+bootblock-$(CONFIG_UART_DEBUG) += uart.c
romstage-y += memmap.c
romstage-y += reset.c
-romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
+romstage-$(CONFIG_UART_DEBUG) += uart.c
ramstage-y += cbmem.c
ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
-ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
+ramstage-$(CONFIG_UART_DEBUG) += uart.c
+
+postcar-y += memmap.c
+postcar-$(CONFIG_UART_DEBUG) += uart.c
CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cannonlake
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 26ccd96..644b603 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -14,6 +14,10 @@
*/
#include <arch/io.h>
+#include <arch/symbols.h>
+#include <assert.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
#include <cbmem.h>
#include <console/console.h>
#include <fsp/util.h>
@@ -25,6 +29,8 @@
asmlinkage void car_stage_entry(void)
{
bool s3wake;
+ struct postcar_frame pcf;
+ uintptr_t top_of_ram;
struct chipset_power_state *ps;
console_init();
@@ -36,7 +42,25 @@
timestamp_add_now(TS_START_ROMSTAGE);
s3wake = ps->prev_sleep_state == ACPI_S3;
fsp_memory_init(s3wake);
- die("Get out from FSP memoryinit. \n");
+ if (postcar_frame_init(&pcf, 1 * KiB))
+ die("Unable to initialize postcar frame.\n");
+
+ /*
+ * We need to make sure ramstage will be run cached. At this
+ * point exact location of ramstage in cbmem is not known.
+ * Instruct postcar to cache 16 megs under cbmem top which is
+ * a safe bet to cover ramstage.
+ */
+ top_of_ram = (uintptr_t) cbmem_top();
+ printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
+ top_of_ram -= 16*MiB;
+ postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
+
+ /* Cache the ROM as WP just below 4GiB. */
+ postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1,
+ CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+
+ run_postcar_phase(&pcf);
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c
index 6f5fb6d..dd121b0 100644
--- a/src/soc/intel/cannonlake/uart.c
+++ b/src/soc/intel/cannonlake/uart.c
@@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
+#define __SIMPLE_DEVICE__
+
#include <assert.h>
#include <console/uart.h>
#include <device/pci_def.h>
@@ -60,8 +62,10 @@
gpio_configure_pads(p->pads, ARRAY_SIZE(p->pads));
}
+#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)
uintptr_t uart_platform_base(int idx)
{
/* We can only have one serial console at a time */
return UART_DEBUG_BASE_ADDRESS;
}
+#endif
--
To view, visit https://review.coreboot.org/20688
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a
Gerrit-Change-Number: 20688
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao at intel.com>
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