[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Skip Spi Flash Lockdown from FSP

[Barnali Sarkar (Code Review)]

Hello Subrata Banik, Balaji Manigandan, build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/20645

to look at the new patch set (#2).

Change subject: soc/intel/skylake: Skip Spi Flash Lockdown from FSP
......................................................................

soc/intel/skylake: Skip Spi Flash Lockdown from FSP

Coreboot was setting SPI FPR register to protect the
mrc_cache data range stored in flash. This programming was being done
after FSP Notify 1.
But, FSP was Locking the SPI by setting FLOCKDN Bit during Notify
phase 1, due to which coreboot was unable to protect that range.

As solution, FSP introduced a new UPD SpiFlashCfgLockDown to skip
the Lockdown of flash on interest of bootloader.
Set that UPD to 0 to skip the Lockdown of FAST_SPI flash from FSP.

The same is being done from Coreboot after End of Post at finalize.c
file.

BUG=b:63049493
BRANCH=none
TEST=FPR can be set properly to protect the mrc_cache range. The
issue reported in the bug doesn't come when both software and
hardware WP is enabled with this patch.

Change-Id: I3ffca2f1b05ab2e4ef631275ef7c3a6e23e393aa
Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
---
M src/soc/intel/skylake/chip_fsp20.c
1 file changed, 8 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/20645/2
-- 
To view, visit https://review.coreboot.org/20645
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I3ffca2f1b05ab2e4ef631275ef7c3a6e23e393aa
Gerrit-Change-Number: 20645
Gerrit-PatchSet: 2
Gerrit-Owner: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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