[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Modify fast_spi_lock_bar function

[Barnali Sarkar (Code Review)]

Hello Subrata Banik, Balaji Manigandan, build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/20643

to look at the new patch set (#2).

Change subject: soc/intel/common/block: Modify fast_spi_lock_bar function
......................................................................

soc/intel/common/block: Modify fast_spi_lock_bar function

Use 16bit write to avoid touching the upper two bytes that may cause
write cycle to fail in case a prior transaction has not completed.

This function sets the WRSDIS(Bit 11) and FLOCKDN (Bit 15) of the
SPIBAR + BIOS_HSFSTS_CTL. While WRSDIS is lockable with FLOCKDN,
writing both in the same cycle is guaranteed to work by design.

Avoid read->modify->write operation not to clear the RW1C bits
unintentionally.

Change-Id: Ia7880aaca0ed64150c994d49786a0a008bbaa98b
Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
M src/soc/intel/common/block/fast_spi/fast_spi_def.h
2 files changed, 10 insertions(+), 4 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/20643/2
-- 
To view, visit https://review.coreboot.org/20643
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ia7880aaca0ed64150c994d49786a0a008bbaa98b
Gerrit-Change-Number: 20643
Gerrit-PatchSet: 2
Gerrit-Owner: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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