[coreboot-gerrit] Change in coreboot[master]: siemens/mc_apl1: Activate ECC for DRAM

[Mario Scheithauer (Code Review)]

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/20634


Change subject: siemens/mc_apl1: Activate ECC for DRAM
......................................................................

siemens/mc_apl1: Activate ECC for DRAM

This mainboard is equipped with DDR3L modules which supports ECC. The
BWG says that for activating ECC the FSP-M parameter MemoryDown must be
set to 5.

Change-Id: Idc68df1e2bae2396c9b9788d4a026a75b7d9119b
Signed-off-by: Mario Scheithauer <mario.scheithauer at siemens.com>
---
M src/mainboard/siemens/mc_apl1/romstage.c
1 file changed, 1 insertion(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/20634/1

diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c
index 3347f23..3462c76 100644
--- a/src/mainboard/siemens/mc_apl1/romstage.c
+++ b/src/mainboard/siemens/mc_apl1/romstage.c
@@ -57,7 +57,7 @@
 	/* DRAM Config settings */
 	memupd->FspmConfig.Package = 0x1;
 	memupd->FspmConfig.Profile = 0x19;
-	memupd->FspmConfig.MemoryDown = 0x1;
+	memupd->FspmConfig.MemoryDown = 0x5;
 	memupd->FspmConfig.DDR3LPageSize = 0x2;
 	memupd->FspmConfig.DDR3LASR = 0x0;
 	memupd->FspmConfig.ScramblerSupport = 0x0;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Idc68df1e2bae2396c9b9788d4a026a75b7d9119b
Gerrit-Change-Number: 20634
Gerrit-PatchSet: 1
Gerrit-Owner: Mario Scheithauer <mario.scheithauer at siemens.com>
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