[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Rectify LPC Lock Enable (LE) bit definition

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20614


Change subject: soc/intel/skylake: Rectify LPC Lock Enable (LE) bit definition
......................................................................

soc/intel/skylake: Rectify LPC Lock Enable (LE) bit definition

LPC pci config register BIOS Control (BC) - offset 0xDC bit 1
is for Lock Down.

Change-Id: I838dd946b8cdb7114f58ccc5d02159f241f0bad0
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/skylake/include/soc/lpc.h
1 file changed, 1 insertion(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/20614/1

diff --git a/src/soc/intel/skylake/include/soc/lpc.h b/src/soc/intel/skylake/include/soc/lpc.h
index b46b8ca..f3541a0 100644
--- a/src/soc/intel/skylake/include/soc/lpc.h
+++ b/src/soc/intel/skylake/include/soc/lpc.h
@@ -51,7 +51,7 @@
 #define LGMR			0x98 /* LPC Generic Memory Range */
 #define BIOS_CNTL		0xdc
 #define  LPC_BC_BILD		(1 << 7) /* BILD */
-#define  LPC_BC_LE		(1 << 2) /* LE */
+#define  LPC_BC_LE		(1 << 1) /* LE */
 #define  LPC_BC_EISS		(1 << 5) /* EISS */
 #define PCCTL			0xE0 /* PCI Clock Control */
 #define CLKRUN_EN		(1 << 0)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I838dd946b8cdb7114f58ccc5d02159f241f0bad0
Gerrit-Change-Number: 20614
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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