[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Call into FSP siliconinit

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/20581


Change subject: soc/intel/cannonlake: Call into FSP siliconinit
......................................................................

soc/intel/cannonlake: Call into FSP siliconinit

The following changes can make system call into FSP siliconinit and exit
from that until payloads.
1. Add frame to call fspsinit.
2. Temporary clear all the USB OC pin to 0 to pass FSP siliconinit.

Change-Id: I1c9c35ececf3c28d7a024f10a5d326700cc8ac49
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/cannonlake/Makefile.inc
A src/soc/intel/cannonlake/chip.c
A src/soc/intel/cannonlake/chip.h
A src/soc/intel/cannonlake/include/soc/ramstage.h
4 files changed, 121 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/20581/1

diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index a5cb463..2b5bd1c 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -16,6 +16,7 @@
 romstage-y += reset.c
 romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
 
+ramstage-y += chip.c
 ramstage-y += memmap.c
 ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
 ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
new file mode 100644
index 0000000..70b4718
--- /dev/null
+++ b/src/soc/intel/cannonlake/chip.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016-2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <chip.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <fsp/api.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <romstage_handoff.h>
+#include <soc/ramstage.h>
+#include <string.h>
+
+void soc_init_pre_device(void *chip_info)
+{
+	/* Perform silicon specific init. */
+	fsp_silicon_init(romstage_handoff_is_resume());
+}
+
+struct chip_operations soc_intel_cannonlake_ops = {
+	CHIP_NAME("Intel Cannonlake")
+	.init		= &soc_init_pre_device,
+};
+
+/* UPD parameters to be initialized before SiliconInit */
+void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
+{
+	int i;
+	FSP_S_CONFIG *params = &supd->FspsConfig;
+
+	/* Set USB OC pin to 0 first */
+	for (i = 0; i < 16; i++) {
+		params->Usb2OverCurrentPin[i] =
+				0;
+	}
+
+	for (i = 0; i < 8; i++) {
+		params->Usb3OverCurrentPin[i] =
+				0;
+	}
+
+	mainboard_silicon_init_params(params);
+}
+
+/* Mainboard GPIO Configuration */
+__attribute__((weak)) void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
new file mode 100644
index 0000000..0219556
--- /dev/null
+++ b/src/soc/intel/cannonlake/chip.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_CHIP_H_
+#define _SOC_CHIP_H_
+
+#include <stdint.h>
+struct soc_intel_cannonlake_config {
+};
+
+typedef struct soc_intel_cannonlake_config config_t;
+
+
+#endif
+
diff --git a/src/soc/intel/cannonlake/include/soc/ramstage.h b/src/soc/intel/cannonlake/include/soc/ramstage.h
new file mode 100644
index 0000000..2927f37
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/ramstage.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_RAMSTAGE_H_
+#define _SOC_RAMSTAGE_H_
+
+#include <chip.h>
+#include <device/device.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+
+#define FSP_SIL_UPD FSP_S_CONFIG
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params);
+void soc_init_pre_device(void *chip_info);
+
+#endif

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1c9c35ececf3c28d7a024f10a5d326700cc8ac49
Gerrit-Change-Number: 20581
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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