[coreboot-gerrit] Change in coreboot[master]: sb/intel/fspi89xx: Fix timestamp code

[Martin Roth (Code Review)]

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20564


Change subject: sb/intel/fspi89xx: Fix timestamp code
......................................................................

sb/intel/fspi89xx: Fix timestamp code

The save_timestamp_to_cmos code was used at Sage before the early
cbmem was available.  Update it to use the standard timestamp calls,
based on the rangeley implementation.

Change-Id: I9a3a6609bdc8d03c4b86951daa1cafddd9c1332e
Signed-off-by: Martin Roth <martinroth at google.com>
---
M src/southbridge/intel/fsp_i89xx/romstage.c
1 file changed, 4 insertions(+), 6 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/20564/1

diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c
index c2b5221..a972bd7 100644
--- a/src/southbridge/intel/fsp_i89xx/romstage.c
+++ b/src/southbridge/intel/fsp_i89xx/romstage.c
@@ -99,9 +99,9 @@
 
 	post_code(0x40);
 
-#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
-	save_timestamp_to_cmos(CMOS_MAIN_START_ADDR, rdtsc());
-#endif
+	timestamp_init(get_initial_timestamp());
+	timestamp_add_now(TS_START_ROMSTAGE);
+
 	pch_enable_lpc();
 
 	/* Enable GPIOs */
@@ -151,9 +151,7 @@
 
 	post_code(0x48);
 
-#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
-	save_timestamp_to_cmos(CMOS_PRE_INITRAM_ADDR, rdtsc());
-#endif
+	timestamp_add_now(TS_BEFORE_INITRAM);
 
   /*
    * Call early init to initialize memory and chipset. This function returns

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9a3a6609bdc8d03c4b86951daa1cafddd9c1332e
Gerrit-Change-Number: 20564
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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