[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Enable smbus based on mainboard config

[Naresh Solanki (Code Review)]

Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/20546


Change subject: soc/intel/skylake: Enable smbus based on mainboard config
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soc/intel/skylake: Enable smbus based on mainboard config

Enable smbus controller based on config in mainboard devicetree.cb

Change-Id: I04c8bc30c03fd8dc7cc8ae239885e740b09e9bc1
Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
---
M src/soc/intel/skylake/romstage/romstage_fsp20.c
1 file changed, 2 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/20546/1

diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 093f7c0..b09ebeb 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -243,6 +243,8 @@
 	m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size;
 	m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size;
 
+	m_cfg->SmbusEnable = config->SmbusEnable;
+
 	mainboard_memory_init_params(mupd);
 }
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I04c8bc30c03fd8dc7cc8ae239885e740b09e9bc1
Gerrit-Change-Number: 20546
Gerrit-PatchSet: 1
Gerrit-Owner: Naresh Solanki <naresh.solanki at intel.com>
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