[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Log wakes due to PCIE root port

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20532 )

Change subject: soc/intel/skylake: Log wakes due to PCIE root port
......................................................................


Patch Set 1: Verified+1

Build Successful 

https://qa.coreboot.org/job/coreboot-gerrit/56818/ : SUCCESS

https://qa.coreboot.org/job/coreboot-checkpatch/12368/ : SUCCESS


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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I879a7c332e62ab598942b29d31bad84619b35ea7
Gerrit-Change-Number: 20532
Gerrit-PatchSet: 1
Gerrit-Owner: Naresh Solanki <naresh.solanki at intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Tue, 11 Jul 2017 13:25:10 +0000
Gerrit-HasComments: No
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