[coreboot-gerrit] Patch set updated for coreboot: google/pyro: Add USB2 phy setting override
Kevin Chiu (Kevin.Chiu@quantatw.com)
gerrit at coreboot.org
Wed Jan 25 17:22:22 CET 2017
Kevin Chiu (Kevin.Chiu at quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18229
-gerrit
commit d026d27a33915c28e6944641826ad50f9b012224
Author: Kevin Chiu <Kevin.Chiu at quantatw.com>
Date: Wed Jan 25 23:06:23 2017 +0800
google/pyro: Add USB2 phy setting override
In order to pass type A USB2 eye diagram,
USB2 port#0/#1 PHY register will need to be overridden.
port#0:
PERPORTPETXISET = 7
PERPORTTXISET = 1
IUSBTXEMPHASISEN = 3
PERPORTTXPEHALF = 0
port#1:
PERPORTPETXISET = 7
PERPORTTXISET = 2
IUSBTXEMPHASISEN = 3
PERPORTTXPEHALF = 0
BUG=chrome-os-partner:59491
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I8e67a6f0192d1c0abf6ec4926c2a17e44c818948
Signed-off-by: Kevin Chiu <Kevin.Chiu at quantatw.com>
---
src/mainboard/google/reef/variants/pyro/devicetree.cb | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb
index f7551d6..e8bd7fa 100644
--- a/src/mainboard/google/reef/variants/pyro/devicetree.cb
+++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb
@@ -105,6 +105,22 @@ chip soc/intel/apollolake
# Minimum SLP S3 assertion width 28ms.
register "slp_s3_assertion_width_usecs" = "28000"
+ # Override USB2 PER PORT register (PORT 0)
+ register "usb2eye[0]" = "{
+ .Usb20PerPortPeTxiSet = 7,
+ .Usb20PerPortTxiSet = 1,
+ .Usb20IUsbTxEmphasisEn = 3,
+ .Usb20PerPortTxPeHalf = 0,
+ }"
+
+ # Override USB2 PER PORT register (PORT 1)
+ register "usb2eye[1]" = "{
+ .Usb20PerPortPeTxiSet = 7,
+ .Usb20PerPortTxiSet = 2,
+ .Usb20IUsbTxEmphasisEn = 3,
+ .Usb20PerPortTxPeHalf = 0,
+ }"
+
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF
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