[coreboot-gerrit] New patch to review for coreboot: google/pyro: Add USB2 phy setting override

[Kevin Chiu (Kevin.Chiu@quantatw.com)]

Kevin Chiu (Kevin.Chiu at quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18229

-gerrit

commit 293c596f92ccc339fc6dd8fd14e10f74d0a38de7
Author: Kevin Chiu <Kevin.Chiu at quantatw.com>
Date:   Wed Jan 25 23:06:23 2017 +0800

    google/pyro: Add USB2 phy setting override
    
    Override USB2 PHY register:
    port#0:
    PERPORTPETXISET = 7
    PERPORTTXISET = 1
    IUSBTXEMPHASISEN = 3
    PERPORTTXPEHALF = 0
    
    port#1:
    PERPORTPETXISET = 7
    PERPORTTXISET = 2
    IUSBTXEMPHASISEN = 3
    PERPORTTXPEHALF = 0
    
    BUG=chrome-os-partner:59491
    BRANCH=reef
    TEST=emerge-pyro coreboot
    Change-Id: I8e67a6f0192d1c0abf6ec4926c2a17e44c818948
    Signed-off-by: Kevin Chiu <Kevin.Chiu at quantatw.com>
---
 src/mainboard/google/reef/variants/pyro/devicetree.cb | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb
index f7551d6..e61f8ec 100644
--- a/src/mainboard/google/reef/variants/pyro/devicetree.cb
+++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb
@@ -223,4 +223,20 @@ chip soc/intel/apollolake
 		end
 		device pci 1f.1 on  end	# - SMBUS
 	end
+
+	# (TYPE C PORT 0)
+        register "usb2eye[0]" = "{
+                .Usb20PerPortPeTxiSet = 7,
+                .Usb20PerPortTxiSet = 1,
+                .Usb20IUsbTxEmphasisEn = 3,
+                .Usb20PerPortTxPeHalf = 0,
+        }"
+
+        # (TYPE C PORT 1)
+        register "usb2eye[1]" = "{
+                .Usb20PerPortPeTxiSet = 7,
+                .Usb20PerPortTxiSet = 2,
+                .Usb20IUsbTxEmphasisEn = 3,
+                .Usb20PerPortTxPeHalf = 0,
+        }"
 end