[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/skylake: Include I2C code in romstage

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 4234ca276419314a0df598c7375c683def67ab1a
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Sat Jan 21 16:55:03 2017 -0800

    soc/intel/skylake: Include I2C code in romstage
    
    The lpss_i2c driver is enabled in romstage, so the SOC needs to
    export the pre-ram compatible I2C controller info, which for
    skylake is in the bootblock/i2c.c file.
    
    This was not causing a compiler error in normal use, but when
    adding I2C debug code in romstage it failed to compile.
    With this added, I can now do I2C transactions in romstage.
    
    Change-Id: I0778b0497d0b6936df47c29b2ce942c8d90cf39b
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://review.coreboot.org/18198
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/18198 for details.

-gerrit