[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: Include I2C code in romstage

[Duncan Laurie (dlaurie@chromium.org)]

Duncan Laurie (dlaurie at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18198

-gerrit

commit 8ad1b37b3a67ca9bf125b9728190f7a672453ab7
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Sat Jan 21 16:55:03 2017 -0800

    soc/intel/skylake: Include I2C code in romstage
    
    The lpss_i2c driver is enabled in romstage, so the SOC needs to
    export the pre-ram compatible I2C controller info, which for
    skylake is in the bootblock/i2c.c file.
    
    This was not causing a compiler error in normal use, but when
    adding I2C debug code in romstage it failed to compile.
    With this added, I can now do I2C transactions in romstage.
    
    Change-Id: I0778b0497d0b6936df47c29b2ce942c8d90cf39b
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/soc/intel/skylake/Makefile.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 3a474e7..4b6fcfc 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -38,6 +38,7 @@ verstage-y += spi.c
 
 romstage-y += flash_controller.c
 romstage-y += gpio.c
+romstage-y += bootblock/i2c.c
 romstage-y += memmap.c
 romstage-y += monotonic_timer.c
 romstage-y += me.c