[coreboot-gerrit] New patch to review for coreboot: google/eve: Enable separate recovery MRC cache
Duncan Laurie (dlaurie@chromium.org)
gerrit at coreboot.org
Sun Jan 22 02:04:49 CET 2017
Duncan Laurie (dlaurie at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18199
-gerrit
commit a6f759eecf1ff7b8c21beba207d9f06b7570033b
Author: Duncan Laurie <dlaurie at chromium.org>
Date: Sat Jan 21 16:57:57 2017 -0800
google/eve: Enable separate recovery MRC cache
In order to get quick boot speeds into recovery enable the
feature that allows for a separate recovery MRC cache.
This requires shuffling the FMAP around a bit in order to
provide another region for the recovery MRC cache. To make
that shuffling easier, group the RW components into another
sub-region so it can use relative addresses.
BUG=chrome-os-partner:58666
TEST=manual testing on eve: check that recovery uses the MRC
cache, and that normal mode does too. Check that if cache is
retrained in recovery mode it is also retrained in normal mode.
Also check that events show up in the log when retrain happens.
Change-Id: I6a9507eb0b919b3af2752e2499904cc62509c06a
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
src/mainboard/google/eve/Kconfig | 2 ++
src/mainboard/google/eve/chromeos.fmd | 31 ++++++++++++++++++-------------
2 files changed, 20 insertions(+), 13 deletions(-)
diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig
index 32c029d..e83e7d9 100644
--- a/src/mainboard/google/eve/Kconfig
+++ b/src/mainboard/google/eve/Kconfig
@@ -18,7 +18,9 @@ config BOARD_SPECIFIC_OPTIONS
config CHROMEOS
select EC_GOOGLE_CHROMEEC_SWITCHES
+ select HAS_RECOVERY_MRC_CACHE
select LID_SWITCH
+ select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
config DRIVERS_I2C_GENERIC
def_bool y
diff --git a/src/mainboard/google/eve/chromeos.fmd b/src/mainboard/google/eve/chromeos.fmd
index 58b6127..bdadcf7 100644
--- a/src/mainboard/google/eve/chromeos.fmd
+++ b/src/mainboard/google/eve/chromeos.fmd
@@ -4,24 +4,29 @@ FLASH at 0xff000000 0x1000000 {
SI_ME at 0x1000 0x1ff000
}
SI_BIOS at 0x200000 0xe00000 {
- RW_SECTION_A at 0x0 0x3f0000 {
+ RW_SECTION_A at 0x0 0x3e8000 {
VBLOCK_A at 0x0 0x10000
- FW_MAIN_A(CBFS)@0x10000 0x3dffc0
- RW_FWID_A at 0x3effc0 0x40
+ FW_MAIN_A(CBFS)@0x10000 0x3d7fc0
+ RW_FWID_A at 0x3e7fc0 0x40
}
- RW_SECTION_B at 0x3f0000 0x3f0000 {
+ RW_SECTION_B at 0x3e8000 0x3e8000 {
VBLOCK_B at 0x0 0x10000
- FW_MAIN_B(CBFS)@0x10000 0x3dffc0
- RW_FWID_B at 0x3effc0 0x40
+ FW_MAIN_B(CBFS)@0x10000 0x3d7fc0
+ RW_FWID_B at 0x3e7fc0 0x40
}
- RW_MRC_CACHE at 0x7e0000 0x10000
- RW_ELOG at 0x7f0000 0x4000
- RW_SHARED at 0x7f4000 0x4000 {
- SHARED_DATA at 0x0 0x2000
- VBLOCK_DEV at 0x2000 0x2000
+ RW_MISC at 0x7d0000 0x30000 {
+ UNIFIED_MRC_CACHE at 0x0 0x20000 {
+ RECOVERY_MRC_CACHE at 0x0 0x10000
+ RW_MRC_CACHE at 0x10000 0x10000
+ }
+ RW_ELOG at 0x20000 0x4000
+ RW_SHARED at 0x24000 0x4000 {
+ SHARED_DATA at 0x0 0x2000
+ VBLOCK_DEV at 0x2000 0x2000
+ }
+ RW_VPD at 0x28000 0x2000
+ RW_NVRAM at 0x2a000 0x6000
}
- RW_VPD at 0x7f8000 0x2000
- RW_NVRAM at 0x7fa000 0x6000
RW_LEGACY(CBFS)@0x800000 0x200000
WP_RO at 0xa00000 0x400000 {
RO_VPD at 0x0 0x4000
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