[coreboot-gerrit] New patch to review for coreboot: mb/lenovo/t400/romstage: Enable D1F0
Patrick Rudolph (siro@das-labor.org)
gerrit at coreboot.org
Sat Jan 21 11:48:15 CET 2017
Patrick Rudolph (siro at das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18195
-gerrit
commit e88e3783d436c9189f2dc3c4f58b0a0a1eb1d1a8
Author: Patrick Rudolph <siro at das-labor.org>
Date: Sat Jan 21 10:45:03 2017 +0100
mb/lenovo/t400/romstage: Enable D1F0
Enable PEG (D1F0) to make sure it can be accessed by raminit().
Change-Id: Ia3c1516c54c28bbe5a127153912c9682e975bea2
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
src/mainboard/lenovo/t400/romstage.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
index d110d4f..b23a5d3 100644
--- a/src/mainboard/lenovo/t400/romstage.c
+++ b/src/mainboard/lenovo/t400/romstage.c
@@ -104,11 +104,14 @@ void mainboard_romstage_entry(unsigned long bist)
sysinfo.enable_igd = 1;
sysinfo.enable_peg = 0;
get_gmch_info(&sysinfo);
- raminit(&sysinfo, s3resume);
const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN);
/* Disable D4F0 (unknown signal controller). */
pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000);
+ /* Enable D1F0 (PEG). */
+ pci_write_config32(MCH_DEV, D0F0_DEVEN, deven | 2);
+
+ raminit(&sysinfo, s3resume);
init_pm(&sysinfo, 0);
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