[coreboot-gerrit] New patch to review for coreboot: google/pyro: Update DPTF settings
Kevin Chiu (Kevin.Chiu@quantatw.com)
gerrit at coreboot.org
Thu Jan 19 08:30:43 CET 2017
Kevin Chiu (Kevin.Chiu at quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18174
-gerrit
commit f5aa52c7bbde8291d4dd5e1fb90bd04a58fb3ae6
Author: Kevin Chiu <Kevin.Chiu at quantatw.com>
Date: Thu Jan 19 15:25:15 2017 +0800
google/pyro: Update DPTF settings
1. Update DPTF CPU/TSR1 passive trigger points.
CPU passive point:80
TSR1 passive point:46
2. Update DPTF TRT Sample Period
TSR1: 8s
BUG=none
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I8fcf750ac17b8894ed3c8704eec62f5071d9cf24
Signed-off-by: Kevin Chiu <Kevin.Chiu at quantatw.com>
---
.../google/reef/variants/pyro/include/variant/acpi/dptf.asl | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl
index f14999c..1423c32 100644
--- a/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl
@@ -14,7 +14,7 @@
* GNU General Public License for more details.
*/
-#define DPTF_CPU_PASSIVE 57
+#define DPTF_CPU_PASSIVE 80
#define DPTF_CPU_CRITICAL 90
#define DPTF_CPU_ACTIVE_AC0 90
#define DPTF_CPU_ACTIVE_AC1 80
@@ -29,7 +29,7 @@
#define DPTF_TSR1_SENSOR_ID 1
#define DPTF_TSR1_SENSOR_NAME "Ambient"
-#define DPTF_TSR1_PASSIVE 55
+#define DPTF_TSR1_PASSIVE 46
#define DPTF_TSR1_CRITICAL 70
#define DPTF_TSR2_SENSOR_ID 2
@@ -61,7 +61,7 @@ Name (DTRT, Package () {
#endif
/* CPU Effect on Temp Sensor 1 */
- Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 550, 0, 0, 0, 0 },
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 80, 0, 0, 0, 0 },
/* CPU Effect on Temp Sensor 2 */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 1200, 0, 0, 0, 0 },
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