[coreboot-gerrit] New patch to review for coreboot: [RFC] Allow to add a second bootblock at a 64K offset for BUC.TS

[Arthur Heymans (arthur@aheymans.xyz)]

Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18148

-gerrit

commit 87e56edbc3d14dee74a275cfac5266c551da771e
Author: Arthur Heymans <arthur at aheymans.xyz>
Date:   Sun Jan 15 14:24:56 2017 +0100

    [RFC] Allow to add a second bootblock at a 64K offset for BUC.TS
    
    This allows to add a second bootblock at an offset of 64K in order for
    it to be used if the BUC.TS bit, RCBA(0x3414)[BITO], is set.
    
    This method is often used to flash coreboot when the vendor BIOS only
    write protects its bootblock at the bottom of flash (e.g. Lenovo
    thinkpad X60 and T60).
    
    TESTED on Thinkpad x200 with BIT0 of RCBA(0x3410) unset (not default
    in coreboot).
    
    Some questions, remarks:
    - How to do this with cbfstool could also simply be documented instead
    of integrated in the build system;
    - Is this Makefile code a good way to achieve this?
    - Kconfig: Should this be board specific instead of southbridge
    specific, since it is mainly aimed at flashing coreboot from vendor BIOS? It
    really depends on the vendor BIOS bootblock if this Backed Up Control
    Top Swap trick works.
    
    Change-Id: I37e288e710edbe41651d09d2a6981a571df69bde
    Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
 Makefile.inc                           |  7 +++++++
 src/southbridge/intel/common/Kconfig   | 14 ++++++++++++++
 src/southbridge/intel/i82801gx/Kconfig |  1 +
 src/southbridge/intel/i82801ix/Kconfig |  1 +
 4 files changed, 23 insertions(+)

diff --git a/Makefile.inc b/Makefile.inc
index c5ce30f..9f0fe28 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -844,6 +844,13 @@ ifeq ($(CONFIG_ARCH_X86),y)
 		-n bootblock \
 		-t bootblock \
 		-b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes)
+ifeq ($(CONFIG_BUCTS_BOOTBLOCK),y)
+	$(CBFSTOOL) $@.tmp add \
+		-f $(objcbfs)/bootblock.bin \
+		-n bootblock_bucts \
+		-t bootblock \
+		-b -$(call int-add,$(call file-size,$(objcbfs)/bootblock.bin) 0x10000) $(cbfs-autogen-attributes)
+endif # ifeq CONFIG_BUCTS_BOOTBLOCK
 else # ifeq ($(CONFIG_ARCH_X86),y)
 	$(CBFSTOOL) $@.tmp write -u \
 		-r BOOTBLOCK \
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig
index 7bc686d..78d7b38 100644
--- a/src/southbridge/intel/common/Kconfig
+++ b/src/southbridge/intel/common/Kconfig
@@ -2,3 +2,17 @@ config SOUTHBRIDGE_INTEL_COMMON
 	def_bool n
 config SOUTHBRIDGE_INTEL_COMMON_GPIO
 	def_bool n
+config HAVE_BUCTS
+	bool
+	default n
+config BUCTS_BOOTBLOCK
+	bool "Include a BUC.TS bootblock"
+	default n
+	depends on HAVE_BUCTS
+	help
+	  Some vendor BIOS only write protect their bootblock.
+	  Using the buc.ts register RCBA[0x3414], it is possible to have
+	  the southbridge look for the bootblock at a 64K offset
+	  instead of the usual top of flash, which might not be
+	  write protected.
+	  Select this to put a 'second' bootblock at a 64K offset.
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index b2265c4..4eb2835 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -24,6 +24,7 @@ config SOUTHBRIDGE_INTEL_I82801GX
 	select HAVE_SMI_HANDLER
 	select COMMON_FADT
 	select SOUTHBRIDGE_INTEL_COMMON_GPIO
+	select HAVE_BUCTS
 
 if SOUTHBRIDGE_INTEL_I82801GX
 
diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig
index e4d1f91..0928a8a 100644
--- a/src/southbridge/intel/i82801ix/Kconfig
+++ b/src/southbridge/intel/i82801ix/Kconfig
@@ -25,6 +25,7 @@ config SOUTHBRIDGE_INTEL_I82801IX
 	select HAVE_USBDEBUG_OPTIONS
 	select SOUTHBRIDGE_INTEL_COMMON_GPIO
 	select HAVE_INTEL_FIRMWARE
+	select HAVE_BUCTS
 
 if SOUTHBRIDGE_INTEL_I82801IX