[coreboot-gerrit] Patch set updated for coreboot: mainboard/google/reef: Ignore SPI IOSTANDBY

[Lijian Zhao (lijian.zhao@intel.com)]

Lijian Zhao (lijian.zhao at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18137

-gerrit

commit add89359c60f5dcb55fab4c3750ee9205f4725cc
Author: Lijian Zhao <lijian.zhao at intel.com>
Date:   Fri Jan 13 14:01:42 2017 -0800

    mainboard/google/reef: Ignore SPI IOSTANDBY
    
    SPI controller need to access flash descriptors/SFDP during s0ix exit,
    so all fast SPI IO can't be put into IOSTANDBY state. For reef, that
    will be FST_SPI_CLK_FB, GPIO_97, GPIO_99, GPIO_100, GPIO_103 and
    GPIO_106.
    
    BUG=chrome-os-partner:61370
    BRANCH=reef
    TEST=Enter s0ix state in OS, after resume run flashrom to read SPI
    content.
    
    Change-Id: I5c59601ec00e93c03dd72a99a739add0950c6a51
    Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
 .../google/reef/variants/baseboard/gpio.c          | 25 +++++++++++-----------
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c
index d5e5917..0c5975a 100644
--- a/src/mainboard/google/reef/variants/baseboard/gpio.c
+++ b/src/mainboard/google/reef/variants/baseboard/gpio.c
@@ -238,20 +238,21 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPIO_92, DN_20K, DEEP),	 /* unused -- strap */
 
 	/* Fast SPI */
-	PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1),	 /* FST_SPI_CS0_B */
-	PAD_CFG_GPI(GPIO_98, UP_20K, DEEP),	 /* FST_SPI_CS1_B -- unused */
-	PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1),	 /* FST_SPI_MOSI_IO0 */
-	PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), /* FST_SPI_MISO_IO1 */
-	PAD_CFG_GPI(GPIO_101, UP_20K, DEEP),	 /* FST_IO2 -- MEM_CONFIG0 */
-	PAD_CFG_GPI(GPIO_102, UP_20K, DEEP),	 /* FST_IO3 -- MEM_CONFIG1 */
-	PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), /* FST_SPI_CLK */
+	PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE),	/* FST_SPI_CS0_B */
+	PAD_CFG_GPI(GPIO_98, UP_20K, DEEP),				/* FST_SPI_CS1_B -- unused */
+	PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE),	/* FST_SPI_MOSI_IO0 */
+	PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE),	/* FST_SPI_MISO_IO1 */
+	PAD_CFG_GPI(GPIO_101, UP_20K, DEEP),				/* FST_IO2 -- MEM_CONFIG0 */
+	PAD_CFG_GPI(GPIO_102, UP_20K, DEEP),				/* FST_IO3 -- MEM_CONFIG1 */
+	PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE),	/* FST_SPI_CLK */
+	PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE), /* FST_SPI_CLK_FB */
+	PAD_CFG_NF_IOSSTATE(GPIO_106, NATIVE, DEEP, NF3, IGNORE),	/* FST_SPI_CS2_N */
 
 	/* SIO_SPI_0 - Used for FP */
-	PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1), /* SIO_SPI_0_CLK */
-	PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1), /* SIO_SPI_0_FS0 */
-	PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */
-	PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1), /* SIO_SPI_0_RXD */
-	PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1), /* SIO_SPI_0_TXD */
+	PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1),			/* SIO_SPI_0_CLK */
+	PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1),			/* SIO_SPI_0_FS0 */
+	PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1),			/* SIO_SPI_0_RXD */
+	PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1),			/* SIO_SPI_0_TXD */
 
 	/* SIO_SPI_1 -- largely unused */
 	PAD_CFG_GPI(GPIO_111, UP_20K, DEEP),	 /* SIO_SPI_1_CLK */