[coreboot-gerrit] New patch to review for coreboot: gru: Tuning USB 2.0 PHY0 and PHY1 host-port

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18126

-gerrit

commit 53965e056e4d6af6450c441b114151fcc66734a2
Author: William wu <wulf at rock-chips.com>
Date:   Mon Jan 9 19:02:39 2017 +0800

    gru: Tuning USB 2.0 PHY0 and PHY1 host-port
    
    The commit 0ba3b2593b0c ("gru: Tuning USB 2.0 PHY to increase
    compatibility") bypass ODT to set the max driver strength for
    the Type-C otg-port, it works well on otg-port when connected
    with USB2.0 devices.
    
    Unfortunately, because the Type-C otg-port and host-port are
    consisted in one USB2 PHY, so bypass ODT will have an effect
    on both host-port and otg-port. I have tested the host-port
    eye-diagram, the result shows that if we bypass ODT, the host-
    port eye-diagram height will become to high, more than 500mv,
    this may cause USB 2.0 high-speed enumeration failure.
    
    This patch bypass ODT for host-port separately, and then we
    can reduce the host-port driver strength without affecting
    the otg-port driver strength.
    
    BRANCH=gru
    BUG=chrome-os-partner:60727
    TEST=Boot system, run 'lsusb' command and check if the usb camera
    and usb bluetooth are on usb 2.0 hub or usb 1.1 hub. If they are
    on usb 1.1 hub, the issue happens. If not, try to run camera app
    and then close camera app, repeat until find that the usb camera
    is on the usb 1.1 hub.
    
    Change-Id: Ib693e2a6f2113c06692a7bfee22d85b67ee3b165
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 5ea7660b7b05080b76fc5ca5af3fa18552a03491
    Original-Change-Id: Ia1f12182929673c5726df9f77f0903469b5c957a
    Original-Signed-off-by: William wu <wulf at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/425739
    Original-Commit-Ready: Douglas Anderson <dianders at chromium.org>
    Original-Tested-by: Douglas Anderson <dianders at chromium.org>
    Original-Tested-by: Inno Park <ih.yoo.park at samsung.com>
    Original-Reviewed-by: Douglas Anderson <dianders at chromium.org>
---
 src/mainboard/google/gru/mainboard.c | 39 +++++++++++++++++++++++++++---------
 1 file changed, 30 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c
index dd986c4..d1ce164 100644
--- a/src/mainboard/google/gru/mainboard.c
+++ b/src/mainboard/google/gru/mainboard.c
@@ -245,39 +245,60 @@ static void usb_power_cycle(int port)
 
 static void setup_usb(void)
 {
-	/* A few magic PHY tuning values that improve eye diagram amplitude
-	 * and make it extra sure we get reliable communication in firmware. */
-	/* Set max ODT compensation voltage and current tuning reference. */
+	/*
+	 * A few magic PHY tuning values that improve eye diagram amplitude
+	 * and make it extra sure we get reliable communication in firmware
+	 * Set max ODT compensation voltage and current tuning reference.
+	 */
 	write32(&rk3399_grf->usbphy0_ctrl[3], RK_CLRSETBITS(0xfff, 0x2e3));
 	write32(&rk3399_grf->usbphy1_ctrl[3], RK_CLRSETBITS(0xfff, 0x2e3));
 
 	if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) {
-		/* Set max pre-emphasis level, only on Kevin PHY0 and PHY1 */
+		/* Set max pre-emphasis level, only on Kevin PHY0 and PHY1. */
 		write32(&rk3399_grf->usbphy0_ctrl[12],
 			RK_CLRSETBITS(0xffff, 0xa7));
 		write32(&rk3399_grf->usbphy1_ctrl[12],
 			RK_CLRSETBITS(0xffff, 0xa7));
 
-		/* Disable the pre-emphasize in eop state and chirp
+		/*
+		 * Disable the pre-emphasize in eop state and chirp
 		 * state to avoid mis-trigger the disconnect detection
-		 * and also avoid high-speed handshake fail */
+		 * and also avoid high-speed handshake fail for PHY0
+		 * and PHY1 consist of otg-port and host-port.
+		 */
 		write32(&rk3399_grf->usbphy0_ctrl[0], RK_CLRBITS(0x3));
 		write32(&rk3399_grf->usbphy1_ctrl[0], RK_CLRBITS(0x3));
 		write32(&rk3399_grf->usbphy0_ctrl[13], RK_CLRBITS(0x3));
 		write32(&rk3399_grf->usbphy1_ctrl[13], RK_CLRBITS(0x3));
 
-		/* ODT auto compensation bypass, set max driver strength */
+		/*
+		 * ODT auto compensation bypass, and set max driver
+		 * strength only for PHY0 and PHY1 otg-port.
+		 */
 		write32(&rk3399_grf->usbphy0_ctrl[2],
 			RK_CLRSETBITS(0x7e << 4, 0x60 << 4));
 		write32(&rk3399_grf->usbphy1_ctrl[2],
 			RK_CLRSETBITS(0x7e << 4, 0x60 << 4));
 
-		/* ODT auto refresh bypass, and set the max
-		 * bias current tuning reference */
+		/*
+		 * ODT auto refresh bypass, and set the max bias current
+		 * tuning reference only for PHY0 and PHY1 otg-port.
+		 */
 		write32(&rk3399_grf->usbphy0_ctrl[3],
 			RK_CLRSETBITS(0x21c, 1 << 4));
 		write32(&rk3399_grf->usbphy1_ctrl[3],
 			RK_CLRSETBITS(0x21c, 1 << 4));
+
+		/*
+		 * ODT auto compensation bypass, and set default driver
+		 * strength only for PHY0 and PHY1 host-port.
+		 */
+		write32(&rk3399_grf->usbphy0_ctrl[15], RK_SETBITS(1 << 10));
+		write32(&rk3399_grf->usbphy1_ctrl[15], RK_SETBITS(1 << 10));
+
+		/* ODT auto refresh bypass only for PHY0 and PHY1 host-port. */
+		write32(&rk3399_grf->usbphy0_ctrl[16], RK_CLRBITS(1 << 9));
+		write32(&rk3399_grf->usbphy1_ctrl[16], RK_CLRBITS(1 << 9));
 	}
 
 	setup_usb_otg0();