[coreboot-gerrit] New patch to review for coreboot: Run sdhci init on an AP in parallel

[Bora Guvendik (bora.guvendik@intel.com)]

Bora Guvendik (bora.guvendik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18108

-gerrit

commit 9b1285b66320e238f099f43824178961d3360c54
Author: Bora Guvendik <bora.guvendik at intel.com>
Date:   Wed Jan 4 17:12:55 2017 -0800

    Run sdhci init on an AP in parallel
    
    Initialize sdhci and setup mmc on AP.
    Put the sdhci in transfer mode and set a flag
    to let payload know that it can just resume
    operations. Let BSP run in parallel and do work
    until it is time to write coreboot tables.
    At that point, make BSP wait for AP to finish up.
    If AP fails to setup sdhci or mmc, let payload
    re-initialize everything.
    
    BUG=chrome-os-partner:59875
    BRANCH=reef
    TEST=None
    
    Change-Id: I86a8b3857685d8638c4cdcd865b16b9454496cb2
    Signed-off-by: Bora Guvendik <bora.guvendik at intel.com>
---
 src/drivers/storage/sdhci.c           |  6 ++++++
 src/drivers/storage/sdhci.h           |  2 ++
 src/lib/coreboot_table.c              |  3 +++
 src/mainboard/google/reef/Kconfig     |  1 +
 src/mainboard/google/reef/mainboard.c | 38 +++++++++++++++++++++++++++++++++++
 5 files changed, 50 insertions(+)

diff --git a/src/drivers/storage/sdhci.c b/src/drivers/storage/sdhci.c
index 54cc54d..88d7180 100644
--- a/src/drivers/storage/sdhci.c
+++ b/src/drivers/storage/sdhci.c
@@ -29,6 +29,8 @@
 #include <timer.h>
 #include <string.h>
 
+atomic_t sdhci_barrier = ATOMIC_INIT(0);
+
 static void sdhci_reset(SdhciHost *host, u8 mask)
 {
 	unsigned long timeout;
@@ -718,4 +720,8 @@ void add_sdhci(SdhciHost *host)
 	host->mmc_ctrlr.b_max = 65535;
 }
 
+atomic_t* get_sdhci_barrier( void )
+{
+	return &sdhci_barrier;
+}
 
diff --git a/src/drivers/storage/sdhci.h b/src/drivers/storage/sdhci.h
index c44edad..6ee7a8f 100644
--- a/src/drivers/storage/sdhci.h
+++ b/src/drivers/storage/sdhci.h
@@ -23,6 +23,7 @@
 
 #include "mmc.h"
 #include <device/pci_ops.h>
+#include <smp/atomic.h>
 
 /*
  * Controller registers
@@ -346,6 +347,7 @@ static inline u8 sdhci_readb(SdhciHost *host, int reg)
 void add_sdhci(SdhciHost *host);
 int sdhci_init(SdhciHost *host);
 SdhciHost* sdhci_get_host_ptr( void );
+atomic_t* get_sdhci_barrier(void);
 
 /* Add SDHCI controller from PCI */
 SdhciHost *new_pci_sdhci_host(struct device *dev,
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 989f8d1..13d0dc9 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -16,6 +16,7 @@
  */
 
 #include <arch/cbconfig.h>
+#include <cpu/x86/mp.h>
 #include <console/console.h>
 #include <console/uart.h>
 #include <ip_checksum.h>
@@ -157,6 +158,8 @@ static void lb_sdhci_host( struct lb_header *header )
 	struct lb_sdhci_host_info  *lb_host;
 	SdhciHost* host_ptr = sdhci_get_host_ptr();
 
+	barrier_wait_timeout(get_sdhci_barrier(),500);
+
 	lb_host = (struct lb_sdhci_host_info *)lb_new_record(header);
 
 	lb_host->tag = LB_TAG_SDHCI_HOST;
diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig
index 0766577a..38af4be 100644
--- a/src/mainboard/google/reef/Kconfig
+++ b/src/mainboard/google/reef/Kconfig
@@ -19,6 +19,7 @@ if BOARD_GOOGLE_BASEBOARD_REEF
 config BASEBOARD_REEF_LAPTOP
 	def_bool n
 	select SYSTEM_TYPE_LAPTOP
+	select DRIVERS_STORAGE
 
 config DRIVER_TPM_I2C_BUS
 	hex
diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c
index 702269c..e7a80cc 100644
--- a/src/mainboard/google/reef/mainboard.c
+++ b/src/mainboard/google/reef/mainboard.c
@@ -28,6 +28,41 @@
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <variant/ec.h>
 #include <variant/gpio.h>
+#include <drivers/storage/sdhci.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mp.h>
+#include <soc/pci_devs.h>
+
+#define EMMC_SD_CLOCK_MIN       400000
+#define EMMC_CLOCK_MAX          200000000
+#define SD_CLOCK_MAX            52000000
+
+static void platform_emmc_init(void)
+{
+	SdhciHost *host;
+
+	host = new_pci_sdhci_host(EMMC_DEV,
+			SDHCI_PLATFORM_NO_EMMC_HS200,
+			EMMC_SD_CLOCK_MIN, EMMC_CLOCK_MAX);
+	sdhci_init(host);
+	mmc_setup_media(&host->mmc_ctrlr,0);
+	host->initialized = 1;
+
+	// Let BSP continue
+	release_barrier(get_sdhci_barrier());
+}
+
+static void run_on_single_ap(void)
+{
+	struct cpu_info *info;
+
+	info = cpu_info();
+
+	if( info->index != 1 )
+		return;
+
+	platform_emmc_init();
+}
 
 static void mainboard_init(void *chip_info)
 {
@@ -35,6 +70,9 @@ static void mainboard_init(void *chip_info)
 	const struct pad_config *pads;
 	size_t num;
 
+	if (mp_run_on_aps(&run_on_single_ap, 1000) < 0)
+		printk(BIOS_ERR, "failed to run sdhci init\n");
+
 	boardid = board_id();
 	printk(BIOS_INFO, "Board ID: %d\n", boardid);