[coreboot-gerrit] Patch merged into coreboot/master: amd/mct/ddr3: Correctly program maximum read latency

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 8fa624784e3d78e67cf7b4e0e72cb2208c399f0f
Author: Timothy Pearson <tpearson at raptorengineering.com>
Date:   Mon Jan 9 14:19:37 2017 -0600

    amd/mct/ddr3: Correctly program maximum read latency
    
    The existing code inadvertently calculated the maximum read
    latency for nonexistent channel 2 instead of for channels
    0 and 1 as intended.  Fix the calls to the maximum read latency
    training function.
    
    Found-by: Coverity Scan #1347354
    Change-Id: If34b204ac73cd20859102cc3b2f40bc99c2ce471
    Signed-off-by: Timothy Pearson <tpearson at raptorengineering.com>
    Reviewed-on: https://review.coreboot.org/18072
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Tested-by: Raptor Engineering Automated Test Stand <noreply at raptorengineeringinc.com>


See https://review.coreboot.org/18072 for details.

-gerrit