[coreboot-gerrit] Patch set updated for coreboot: nb/intel/945gc: Hardcode the integrated graphic frequencies

Arthur Heymans (arthur@aheymans.xyz) gerrit at coreboot.org
Tue Jan 10 16:17:19 CET 2017


Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17981

-gerrit

commit ed09afcef8f0a24794ab819ff41d3022b2ec5cd4
Author: Arthur Heymans <arthur at aheymans.xyz>
Date:   Wed Dec 28 21:20:45 2016 +0100

    nb/intel/945gc: Hardcode the integrated graphic frequencies
    
    The code to set the igd frequencies is written with the mobile version
    of the 945 chipset in mind and seems to cause cause strange igd
    related problems on the desktop versions.
    
    Some possible problems are:
    * on 800MHz fsb CPUs the igd sometimes has artifacts on the screen;
    * on 800MHz fsb CPU memtest results vary a lot;
    * since a commit 45e11aa0a5 "Add/Combine Broadwell Chromebooks using
      variant board scheme" that does not affect this northbridge, the
      display shows garbage as soon as Linux (4.8) modesets the display.
    
    A fix is to hardcode the core display and render clocks to their
    maximum, potentially also improving graphical performance.
    Vendor bios on all boards in coreboot with this northbridge have the
    same value in this PCI config address.
    
    TESTED on P5GC-MX (display works fine again in Linux) and
    user reports of it making GA-945GCM-S2L run more stable.
    
    Change-Id: I8b046edbc952631d9b79023e3d385160ff682c24
    Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
 src/northbridge/intel/i945/raminit.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index a4a1eaf..f9ba37b 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -3116,8 +3116,14 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses)
 	/* Program PLL settings */
 	sdram_program_pll_settings(&sysinfo);
 
-	/* Program Graphics Frequency */
-	sdram_program_graphics_frequency(&sysinfo);
+	/*
+	 * Program Graphics Frequency
+	 * Set core display and render clock on 945GC to the max
+	 */
+	if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
+		sdram_program_graphics_frequency(&sysinfo);
+	else
+		pci_write_config16(PCI_DEV(0, 2, 0), GCFC, 0x0534);
 
 	/* Program System Memory Frequency */
 	sdram_program_memory_frequency(&sysinfo);



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