[coreboot-gerrit] Patch set updated for coreboot: driver/intel/fsp1_1: Fix boot failure for non-verstage case

Mon Jan 9 06:58:50 CET 2017

Boon Tiong Teo (boon.tiong.teo at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17976

-gerrit

commit ba6d1ffcdfae065932dcfcf40a52cd5665d4dc0d
Author: Teo Boon Tiong <boon.tiong.teo at intel.com>
Date:   Wed Dec 28 18:56:26 2016 +0800

    driver/intel/fsp1_1: Fix boot failure for non-verstage case
    
        Currently car_stage_entry is defined only in romstage_after_verstage and
        as a result when SEPARATE_VERSTAGE is not selected, there is no
        entry point into romstage and romstage will not started at all.
    
        The solution is move out romstage_after_verstage.S from fsp1.1 driver
        to skylake/romstage. And add CONFIG_C_ENVIRONMENT_BOOTBLOCK and
        CONFIG_PLATFORM_USES_FSP1_1 to fix the build and boot issue with this
        change.
    
        Beside that, rename the romstage_after_verstage to car_stage_c_entry
        in more appropriate naming convention after this fix.
    
        Tested on Skylake Saddle Brook (Fsp 1.1) and Kabelyake Rvp11 (Fsp 2.0),
        romstage can be started successfully.
    
    Change-Id: I1cd2cf5655fdff6e23b7b76c3974e7dfd3835efd
    Signed-off-by: Teo Boon Tiong <boon.tiong.teo at intel.com>
---
 src/drivers/intel/fsp1_1/Makefile.inc              |  1 -
 src/drivers/intel/fsp1_1/car.c                     |  2 +-
 src/drivers/intel/fsp1_1/include/fsp/car.h         |  2 +-
 src/drivers/intel/fsp1_1/romstage_after_verstage.S | 38 --------------------
 src/soc/intel/skylake/romstage/Makefile.inc        |  1 +
 src/soc/intel/skylake/romstage/car_stage_entry.S   | 40 ++++++++++++++++++++++
 6 files changed, 43 insertions(+), 41 deletions(-)

diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
index 4088293..e2f75ee 100644
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -28,7 +28,6 @@ romstage-y += fsp_util.c
 romstage-y += hob.c
 romstage-y += raminit.c
 romstage-y += romstage.c
-romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S
 romstage-y += stack.c
 romstage-y += stage_cache.c
 romstage-$(CONFIG_MMA) += mma_core.c
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index 1a5f9a8..789d3d8 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -68,7 +68,7 @@ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params)
 }
 
 /* Entry point taken when romstage is called after a separate verstage. */
-asmlinkage void *romstage_after_verstage(void)
+asmlinkage void *car_stage_c_entry(void)
 {
 	/* Need to locate the current FSP_INFO_HEADER. The cache-as-ram
 	 * is still enabled. We can directly access work buffer here. */
diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h
index 88dca9a..499039a 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/car.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/car.h
@@ -32,7 +32,7 @@ struct cache_as_ram_params {
 /* Entry points from the cache-as-ram assembly code. */
 asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params);
 asmlinkage void after_cache_as_ram(void *chipset_context);
-asmlinkage void *romstage_after_verstage(void);
+asmlinkage void *car_stage_c_entry(void);
 /* Per stage calls from the above two functions. The void * return from
  * cache_as_ram_stage_main() is the stack pointer to use in RAM after
  * exiting cache-as-ram mode. */
diff --git a/src/drivers/intel/fsp1_1/romstage_after_verstage.S b/src/drivers/intel/fsp1_1/romstage_after_verstage.S
deleted file mode 100644
index 2a3372f..0000000
--- a/src/drivers/intel/fsp1_1/romstage_after_verstage.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define LHLT_DELAY	0x50000		/* I/O delay between post codes on failure */
-
-.text
-.global car_stage_entry
-car_stage_entry:
-	call	romstage_after_verstage
-	#include "after_raminit.S"
-
-	movb	$0x69, %ah
-	jmp	.Lhlt
-
-.Lhlt:
-	xchg	%al, %ah
-#if IS_ENABLED(CONFIG_POST_IO)
-	outb	%al, $CONFIG_POST_IO_PORT
-#else
-	post_code(POST_DEAD_CODE)
-#endif
-	movl	$LHLT_DELAY, %ecx
-.Lhlt_Delay:
-	outb	%al, $0xED
-	loop	.Lhlt_Delay
-	jmp	.Lhlt
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index 877712f..c6f0057 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -1,6 +1,7 @@
 verstage-y += power_state.c
 
 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += car_stage.S
+romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += car_stage_entry.S
 romstage-y += pmc.c
 romstage-y += power_state.c
 romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c
diff --git a/src/soc/intel/skylake/romstage/car_stage_entry.S b/src/soc/intel/skylake/romstage/car_stage_entry.S
new file mode 100644
index 0000000..923a346
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/car_stage_entry.S
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* I/O delay between post codes on failure */
+#define	LHLT_DELAY	0x50000
+
+.text
+.global car_stage_entry
+car_stage_entry:
+	call	car_stage_c_entry
+	#include "src/drivers/intel/fsp1_1/after_raminit.S"
+
+
+	movb	$0x69, %ah
+	jmp	.Lhlt
+
+.Lhlt:
+	xchg	%al, %ah
+#if IS_ENABLED(CONFIG_POST_IO)
+	outb	%al, $CONFIG_POST_IO_PORT
+#else
+	post_code(POST_DEAD_CODE)
+#endif
+	movl	$LHLT_DELAY, %ecx
+.Lhlt_Delay:
+	outb	%al, $0xED
+	loop	.Lhlt_Delay
+	jmp	.Lhlt

