[coreboot-gerrit] Patch set updated for coreboot: src/cpu/intel/speedstep/acpi.c: Add "FIXME" comment

[HAOUAS Elyes (ehaouas@noos.fr)]

HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18056

-gerrit

commit 3e945a7b2e44985a34ac12f614d8a69fe2214eaa
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date:   Sun Jan 8 11:17:17 2017 +0100

    src/cpu/intel/speedstep/acpi.c: Add "FIXME" comment
    
    MSR(0x2c) provides information about FSB frequency
    for Pentium 4.
    
    Change-Id: I2ba6c446f77184e6dbabd4194a3dd2fdd665b056
    Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
 src/cpu/intel/speedstep/acpi.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index d85e487..b1125b8 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -49,6 +49,11 @@ static int determine_total_number_of_cores(void)
  */
 static int get_fsb(void)
 {
+
+	/* FIXME: we probably need to detect the CPU and
+	 * read the right MSR register to have the right FSB.
+	* Example: for Pentium 4 we should read MSR at 0x2c
+	*/
 	const u32 fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7;
 	switch (fsbcode) {
 		case 0: return  800; /*  / 3 == 266 */