[coreboot-gerrit] Patch set updated for coreboot: cpu/intel/speedstep/acpi.c: Add Netburst CPUs

[HAOUAS Elyes (ehaouas@noos.fr)]

HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18019

-gerrit

commit 0ee3647308cf2a829197be4f75b00da52865edea
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date:   Sat Jan 7 19:51:09 2017 +0100

    cpu/intel/speedstep/acpi.c: Add Netburst CPUs
    
    MSR(0x2c) provides information about FSB frequency.
    
    Change-Id: I42b0dcfdd62e07422acb77462aefc2d9b62fba19
    Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
 src/cpu/intel/speedstep/acpi.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index d85e487..8936eee 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -49,7 +49,21 @@ static int determine_total_number_of_cores(void)
  */
 static int get_fsb(void)
 {
-	const u32 fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7;
+	u32 fsbcode;
+	const u32 eax = cpuid_ext(0x01, 0).eax;
+	const u32 ecx = cpuid_ext(0x01, 0).ecx;
+	msr_t msr;
+
+	/* Handle Netburst based processors if EIST supported */
+	if ((((eax >> 8) & 0xf) == 0xf) &&
+	    (((eax >> 20) & 0xff) == 0) &&
+	    (((ecx >> 7) & 1) == 1)) {
+		msr = rdmsr(0x2c);
+		fsbcode = (msr.lo >> 16) & 7;
+	} else {
+		fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7;
+	}
+
 	switch (fsbcode) {
 		case 0: return  800; /*  / 3 == 266 */
 		case 1: return  400; /*  / 3 == 133 */