[coreboot-gerrit] New patch to review for coreboot: binaryPI boards: Drop any ACPI S3 support
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Sun Feb 26 10:25:03 CET 2017
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18500
-gerrit
commit 0be66b7277a33e0f80aabf4a9fa043b33f0238f2
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Sun Feb 26 10:11:21 2017 +0200
binaryPI boards: Drop any ACPI S3 support
None of the boards currently have HAVE_ACPI_RESUME and
and ACPI S3 support calls should not appear under board
directories anyways.
Change-Id: I1abd40ddba64be25b823abf801988863950c1eb5
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/mainboard/amd/bettong/mainboard.c | 3 ---
src/mainboard/amd/bettong/romstage.c | 32 +++++++------------------
src/mainboard/amd/db-ft3b-lc/mainboard.c | 4 ----
src/mainboard/amd/db-ft3b-lc/romstage.c | 34 ++++++++-------------------
src/mainboard/amd/gardenia/mainboard.c | 3 ---
src/mainboard/amd/gardenia/romstage.c | 32 +++++++------------------
src/mainboard/amd/lamar/mainboard.c | 7 ------
src/mainboard/amd/lamar/romstage.c | 31 +++++++------------------
src/mainboard/amd/olivehillplus/mainboard.c | 4 ----
src/mainboard/amd/olivehillplus/romstage.c | 36 +++++++++--------------------
src/mainboard/bap/ode_e21XX/mainboard.c | 4 ----
src/mainboard/bap/ode_e21XX/romstage.c | 36 +++++++++--------------------
src/mainboard/pcengines/apu2/mainboard.c | 4 ----
src/mainboard/pcengines/apu2/romstage.c | 36 +++++++++--------------------
14 files changed, 67 insertions(+), 199 deletions(-)
diff --git a/src/mainboard/amd/bettong/mainboard.c b/src/mainboard/amd/bettong/mainboard.c
index c31f5b7..11d6084 100644
--- a/src/mainboard/amd/bettong/mainboard.c
+++ b/src/mainboard/amd/bettong/mainboard.c
@@ -84,9 +84,6 @@ static void bettong_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
-
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c
index 6b12afc..7930c89 100644
--- a/src/mainboard/amd/bettong/romstage.c
+++ b/src/mainboard/amd/bettong/romstage.c
@@ -20,7 +20,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/car.h>
-#include <cpu/amd/pi/s3_resume.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <southbridge/amd/pi/hudson/hudson.h>
@@ -28,9 +27,6 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
/* Must come first to enable PCI MMCONF. */
amd_initmmio();
@@ -63,31 +59,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
AGESAWRAPPER(amdinitearly);
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- AGESAWRAPPER(amdinitpost);
- post_code(0x41);
- AGESAWRAPPER(amdinitenv);
- /* TODO: Disable cache is not ok. */
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- AGESAWRAPPER(amdinitresume);
-
- AGESAWRAPPER(amds3laterestore);
- post_code(0x61);
- prepare_for_resume();
- }
-
- if (s3resume || acpi_is_wakeup_s4()) {
+ if (acpi_is_wakeup_s4()) {
outb(0xEE, PM_INDEX);
outb(0x8, PM_DATA);
}
+ post_code(0x40);
+ AGESAWRAPPER(amdinitpost);
+ post_code(0x41);
+ AGESAWRAPPER(amdinitenv);
+ /* TODO: Disable cache is not ok. */
+ disable_cache_as_ram();
+
post_code(0x50);
copy_and_run();
diff --git a/src/mainboard/amd/db-ft3b-lc/mainboard.c b/src/mainboard/amd/db-ft3b-lc/mainboard.c
index 6f8742c..419a57d 100644
--- a/src/mainboard/amd/db-ft3b-lc/mainboard.c
+++ b/src/mainboard/amd/db-ft3b-lc/mainboard.c
@@ -17,7 +17,6 @@
#include <arch/acpi.h>
#include <arch/io.h>
#include <console/console.h>
-#include <cpu/amd/pi/s3_resume.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
@@ -125,9 +124,6 @@ static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
-
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}
diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c
index 79cc0f9..0ba1c1d 100644
--- a/src/mainboard/amd/db-ft3b-lc/romstage.c
+++ b/src/mainboard/amd/db-ft3b-lc/romstage.c
@@ -17,7 +17,6 @@
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp_def.h>
@@ -31,7 +30,6 @@
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>
-#include <cpu/amd/pi/s3_resume.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -77,28 +75,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
AGESAWRAPPER(amdinitearly);
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- AGESAWRAPPER(amdinitpost);
-
- post_code(0x41);
- AGESAWRAPPER(amdinitenv);
- /*
- If code hangs here, please check cahaltasm.S
- */
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- AGESAWRAPPER(amdinitresume);
-
- AGESAWRAPPER(amds3laterestore);
-
- post_code(0x61);
- prepare_for_resume();
- }
+
+ post_code(0x40);
+ AGESAWRAPPER(amdinitpost);
+
+ post_code(0x41);
+ AGESAWRAPPER(amdinitenv);
+ /*
+ If code hangs here, please check cahaltasm.S
+ */
+ disable_cache_as_ram();
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c
index 7ebe087..acc9b7c 100644
--- a/src/mainboard/amd/gardenia/mainboard.c
+++ b/src/mainboard/amd/gardenia/mainboard.c
@@ -84,9 +84,6 @@ static void gardenia_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
-
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}
diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c
index eca9d3b..3d65cc2 100644
--- a/src/mainboard/amd/gardenia/romstage.c
+++ b/src/mainboard/amd/gardenia/romstage.c
@@ -20,7 +20,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/car.h>
-#include <cpu/amd/pi/s3_resume.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <southbridge/amd/pi/hudson/hudson.h>
@@ -28,9 +27,6 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
amd_initmmio();
hudson_lpc_port80();
@@ -62,31 +58,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
AGESAWRAPPER(amdinitearly);
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- AGESAWRAPPER(amdinitpost);
- post_code(0x41);
- AGESAWRAPPER(amdinitenv);
- /* TODO: Disable cache is not ok. */
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- AGESAWRAPPER(amdinitresume);
-
- AGESAWRAPPER(amds3laterestore);
- post_code(0x61);
- prepare_for_resume();
- }
-
- if (s3resume || acpi_is_wakeup_s4()) {
+ if (acpi_is_wakeup_s4()) {
outb(0xEE, PM_INDEX);
outb(0x8, PM_DATA);
}
+ post_code(0x40);
+ AGESAWRAPPER(amdinitpost);
+ post_code(0x41);
+ AGESAWRAPPER(amdinitenv);
+ /* TODO: Disable cache is not ok. */
+ disable_cache_as_ram();
+
post_code(0x50);
copy_and_run();
diff --git a/src/mainboard/amd/lamar/mainboard.c b/src/mainboard/amd/lamar/mainboard.c
index 25e685b..4e010fc 100644
--- a/src/mainboard/amd/lamar/mainboard.c
+++ b/src/mainboard/amd/lamar/mainboard.c
@@ -20,7 +20,6 @@
#include <device/pci_def.h>
#include <arch/acpi.h>
#include <northbridge/amd/pi/BiosCallOuts.h>
-#include <cpu/amd/pi/s3_resume.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
@@ -147,12 +146,6 @@ static void pirq_setup(void)
static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
- /*
- * The mainboard is the first place that we get control in ramstage. Check
- * for S3 resume and call the approriate AGESA/CIMx resume functions.
- */
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index bda8c0f..5530a25 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -17,7 +17,6 @@
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp_def.h>
@@ -32,7 +31,6 @@
#include <cpu/x86/lapic.h>
#include <southbridge/amd/common/amd_defs.h>
#include <southbridge/amd/pi/hudson/hudson.h>
-#include <cpu/amd/pi/s3_resume.h>
#include "cbmem.h"
#include "superio/fintek/f81216h/f81216h.h"
@@ -88,29 +86,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
AGESAWRAPPER(amdinitearly);
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- AGESAWRAPPER(amdinitpost);
-
- post_code(0x41);
- AGESAWRAPPER(amdinitenv);
- /*
- If code hangs here, please check cahaltasm.S
- */
- disable_cache_as_ram();
- }
- else if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- AGESAWRAPPER(amdinitresume);
- AGESAWRAPPER(amds3laterestore);
+ post_code(0x40);
+ AGESAWRAPPER(amdinitpost);
- post_code(0x61);
- prepare_for_resume();
- }
+ post_code(0x41);
+ AGESAWRAPPER(amdinitenv);
+ /*
+ If code hangs here, please check cahaltasm.S
+ */
+ disable_cache_as_ram();
post_code(0x50);
copy_and_run();
diff --git a/src/mainboard/amd/olivehillplus/mainboard.c b/src/mainboard/amd/olivehillplus/mainboard.c
index 1e82768..8693737 100644
--- a/src/mainboard/amd/olivehillplus/mainboard.c
+++ b/src/mainboard/amd/olivehillplus/mainboard.c
@@ -20,7 +20,6 @@
#include <device/pci_def.h>
#include <arch/acpi.h>
#include <northbridge/amd/pi/BiosCallOuts.h>
-#include <cpu/amd/pi/s3_resume.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
@@ -31,9 +30,6 @@
static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 534a8e5..c98ae25 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -17,7 +17,6 @@
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp_def.h>
@@ -31,7 +30,6 @@
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>
-#include <cpu/amd/pi/s3_resume.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -87,29 +85,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
AGESAWRAPPER(amdinitearly);
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- AGESAWRAPPER(amdinitpost);
-
- //PspMboxBiosCmdDramInfo();
- post_code(0x41);
- AGESAWRAPPER(amdinitenv);
- /*
- If code hangs here, please check cahaltasm.S
- */
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- AGESAWRAPPER(amdinitresume);
-
- AGESAWRAPPER(amds3laterestore);
-
- post_code(0x61);
- prepare_for_resume();
- }
+
+ post_code(0x40);
+ AGESAWRAPPER(amdinitpost);
+
+ //PspMboxBiosCmdDramInfo();
+ post_code(0x41);
+ AGESAWRAPPER(amdinitenv);
+ /*
+ If code hangs here, please check cahaltasm.S
+ */
+ disable_cache_as_ram();
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
diff --git a/src/mainboard/bap/ode_e21XX/mainboard.c b/src/mainboard/bap/ode_e21XX/mainboard.c
index 1e82768..8693737 100644
--- a/src/mainboard/bap/ode_e21XX/mainboard.c
+++ b/src/mainboard/bap/ode_e21XX/mainboard.c
@@ -20,7 +20,6 @@
#include <device/pci_def.h>
#include <arch/acpi.h>
#include <northbridge/amd/pi/BiosCallOuts.h>
-#include <cpu/amd/pi/s3_resume.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
@@ -31,9 +30,6 @@
static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c
index 5deeaa8..d8342c9 100644
--- a/src/mainboard/bap/ode_e21XX/romstage.c
+++ b/src/mainboard/bap/ode_e21XX/romstage.c
@@ -17,7 +17,6 @@
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp_def.h>
@@ -31,7 +30,6 @@
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>
-#include <cpu/amd/pi/s3_resume.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f81866d/f81866d.h>
@@ -81,29 +79,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
AGESAWRAPPER(amdinitearly);
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- AGESAWRAPPER(amdinitpost);
-
- //PspMboxBiosCmdDramInfo();
- post_code(0x41);
- AGESAWRAPPER(amdinitenv);
- /*
- If code hangs here, please check cahaltasm.S
- */
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- AGESAWRAPPER(amdinitresume);
-
- AGESAWRAPPER(amds3laterestore);
-
- post_code(0x61);
- prepare_for_resume();
- }
+
+ post_code(0x40);
+ AGESAWRAPPER(amdinitpost);
+
+ //PspMboxBiosCmdDramInfo();
+ post_code(0x41);
+ AGESAWRAPPER(amdinitenv);
+ /*
+ If code hangs here, please check cahaltasm.S
+ */
+ disable_cache_as_ram();
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c
index d2ab638..043bc17 100644
--- a/src/mainboard/pcengines/apu2/mainboard.c
+++ b/src/mainboard/pcengines/apu2/mainboard.c
@@ -16,7 +16,6 @@
#include <arch/acpi.h>
#include <arch/io.h>
#include <console/console.h>
-#include <cpu/amd/pi/s3_resume.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
@@ -183,9 +182,6 @@ static void mainboard_enable(device_t dev)
//
pm_write16 ( PM_S_STATE_CONTROL, pm_read16( PM_S_STATE_CONTROL ) | (1 << 14));
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
-
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index f8ed63c..a0d925f 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -17,7 +17,6 @@
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp_def.h>
@@ -31,7 +30,6 @@
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>
-#include <cpu/amd/pi/s3_resume.h>
#include <Fch/Fch.h>
#include "gpio_ftns.h"
@@ -82,29 +80,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
AGESAWRAPPER(amdinitearly);
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- AGESAWRAPPER(amdinitpost);
-
- //PspMboxBiosCmdDramInfo();
- post_code(0x41);
- AGESAWRAPPER(amdinitenv);
- /*
- If code hangs here, please check cahaltasm.S
- */
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- AGESAWRAPPER(amdinitresume);
-
- AGESAWRAPPER(amds3laterestore);
-
- post_code(0x61);
- prepare_for_resume();
- }
+
+ post_code(0x40);
+ AGESAWRAPPER(amdinitpost);
+
+ //PspMboxBiosCmdDramInfo();
+ post_code(0x41);
+ AGESAWRAPPER(amdinitenv);
+ /*
+ If code hangs here, please check cahaltasm.S
+ */
+ disable_cache_as_ram();
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
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