[coreboot-gerrit] Patch set updated for coreboot: mainboard/intel/leafhill: Clean up
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Sat Feb 25 04:35:40 CET 2017
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18479
-gerrit
commit fce6a6589f78f5b9410de4697ca43d50064b15f0
Author: Andrey Petrov <andrey.petrov at intel.com>
Date: Thu Feb 23 14:10:11 2017 -0800
mainboard/intel/leafhill: Clean up
This patch tries to clean the code by:
o removing duplication of LPC GPIO pads
o removing incorrect definitions from devicetree
o removing irrelevant entries from FMD file
Also adds vital defaults in Kconfig so it is possible to build
an image.
Change-Id: Id9913f3b053189166392271152ce5300d82a7de8
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
src/mainboard/intel/leafhill/Kconfig | 62 +++++-
src/mainboard/intel/leafhill/Makefile.inc | 1 +
src/mainboard/intel/leafhill/brd_gpio.h | 15 +-
src/mainboard/intel/leafhill/devicetree.cb | 259 ++++--------------------
src/mainboard/intel/leafhill/leafhill.fmd | 40 ----
src/mainboard/intel/leafhill/leafhill.fmd.16384 | 14 ++
src/mainboard/intel/leafhill/leafhill.fmd.8192 | 14 ++
7 files changed, 132 insertions(+), 273 deletions(-)
diff --git a/src/mainboard/intel/leafhill/Kconfig b/src/mainboard/intel/leafhill/Kconfig
index ddef0e7..2ec2e03 100644
--- a/src/mainboard/intel/leafhill/Kconfig
+++ b/src/mainboard/intel/leafhill/Kconfig
@@ -4,11 +4,7 @@ config BOARD_SPECIFIC_OPTIONS
def_bool y
select SOC_INTEL_APOLLOLAKE
select BOARD_ROMSIZE_KB_16384
- select DRIVERS_I2C_HID
select HAVE_ACPI_TABLES
-# select HAVE_INTEL_FIRMWARE
-# select HAVE_ME_BIN
-# select LOCK_MANAGEMENT_ENGINE
config MAINBOARD_DIR
string
@@ -22,4 +18,62 @@ config MAINBOARD_PART_NUMBER
string
default "Leafhill"
+config MAINBOARD_VENDOR
+ string
+ default "Intel"
+
+config FMDFILE
+ string
+ default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/leafhill.fmd.$(CONFIG_COREBOOT_ROMSIZE_KB)"
+
+config UART_FOR_CONSOLE
+ int
+ default 2
+
+config NEED_IFWI
+ def_bool y
+
+config IFWI_FMAP_NAME
+ string
+ default "IFWI"
+
+config IFWI_FILE_NAME
+ string
+ default "3rdparty/blobs/mainboard/intel/leafhill/fitimage.bin"
+
+config HAVE_IFWI
+ def_bool y
+
+config IFD_BIN_PATH
+ string
+ default "3rdparty/blobs/mainboard/intel/leafhill/descriptor.bin"
+
+config HAVE_IFD_BIN
+ def_bool y
+
+config SOC_UART_DEBUG
+ def_bool y
+
+config FSP_M_FILE
+ string
+ default "3rdparty/blobs/mainboard/intel/leafhill/FSP-M.Fv"
+
+config FSP_S_FILE
+ string
+ default "3rdparty/blobs/mainboard/intel/leafhill/FSP-S.Fv"
+
+config PLATFORM_USES_FSP2_0
+ def_bool y
+
+config ADD_FSP_BINARIES
+ def_bool y
+
+config FSP_S_CBFS
+ string
+ default "fsps.bin"
+
+config FSP_M_CBFS
+ string
+ default "fspm.bin"
+
endif # BOARD_INTEL_LEAFHILL
diff --git a/src/mainboard/intel/leafhill/Makefile.inc b/src/mainboard/intel/leafhill/Makefile.inc
index 9e3e892..c3077e7 100644
--- a/src/mainboard/intel/leafhill/Makefile.inc
+++ b/src/mainboard/intel/leafhill/Makefile.inc
@@ -1,3 +1,4 @@
bootblock-y += bootblock.c
+romstage-y += romstage.c
ramstage-y += mainboard.c
diff --git a/src/mainboard/intel/leafhill/brd_gpio.h b/src/mainboard/intel/leafhill/brd_gpio.h
index 33b839b..18d130b 100644
--- a/src/mainboard/intel/leafhill/brd_gpio.h
+++ b/src/mainboard/intel/leafhill/brd_gpio.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved.
+ * Copyright (C) 2017 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -15,8 +15,6 @@
#include <soc/gpio.h>
-#if ENV_ROMSTAGE
-
static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPIO_134, NATIVE, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */
PAD_CFG_NF(GPIO_135, NATIVE, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */
@@ -48,15 +46,4 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1),
PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1),
- PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1),
- PAD_CFG_NF(LPC_CLKOUT0, NATIVE, DEEP, NF1),
- PAD_CFG_NF(LPC_CLKOUT1, NATIVE, DEEP, NF1),
- PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1),
- PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1),
- PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1),
- PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1),
- PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1),
- PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1),
};
-
-#endif
diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb
index b0c82e2..2a284d2 100644
--- a/src/mainboard/intel/leafhill/devicetree.cb
+++ b/src/mainboard/intel/leafhill/devicetree.cb
@@ -1,227 +1,56 @@
chip soc/intel/apollolake
- device cpu_cluster 0 on
- device lapic 0 on end
- end
-
- register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
- # Disable unused clkreq of PCIe root ports
+ register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED"
register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
- # GPIO for PERST_0
- # If the Board has PERST_0 signal, assign the GPIO
- # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
- register "prt0_gpio" = "GPIO_122"
-
- # EMMC TX DATA Delay 1
- # Refer to EDS-Vol2-22.3.
- # [14:8] steps of delay for HS400, each 125ps.
- # [6:0] steps of delay for SDR104/HS200, each 125ps.
- register "emmc_tx_data_cntl1" = "0x0C16"
-
- # EMMC TX DATA Delay 2
- # Refer to EDS-Vol2-22.3.
- # [30:24] steps of delay for SDR50, each 125ps.
- # [22:16] steps of delay for DDR50, each 125ps.
- # [14:8] steps of delay for SDR25/HS50, each 125ps.
- # [6:0] steps of delay for SDR12, each 125ps.
- register "emmc_tx_data_cntl2" = "0x28162828"
-
- # EMMC RX CMD/DATA Delay 1
- # Refer to EDS-Vol2-22.3.
- # [30:24] steps of delay for SDR50, each 125ps.
- # [22:16] steps of delay for DDR50, each 125ps.
- # [14:8] steps of delay for SDR25/HS50, each 125ps.
- # [6:0] steps of delay for SDR12, each 125ps.
- register "emmc_rx_cmd_data_cntl1" = "0x00181717"
-
- # EMMC RX CMD/DATA Delay 2
- # Refer to EDS-Vol2-22.3.
- # [17:16] stands for Rx Clock before Output Buffer
- # [14:8] steps of delay for Auto Tuning Mode, each 125ps.
- # [6:0] steps of delay for HS200, each 125ps.
- register "emmc_rx_cmd_data_cntl2" = "0x10008"
-
- # Enable DPTF
- register "dptf_enable" = "1"
-
- # PL1 override 12000 mW: the energy calculation is wrong with the
- # current VR solution. Experiments show that SoC TDP max (6W) can
- # be reached when RAPL PL1 is set to 12W.
- register "tdp_pl1_override_mw" = "12000"
- # Set RAPL PL2 to 15W.
- register "tdp_pl2_override_mw" = "15000"
-
- # Enable Audio Clock and Power gating
- register "hdaudio_clk_gate_enable" = "1"
- register "hdaudio_pwr_gate_enable" = "1"
- register "hdaudio_bios_config_lockdown" = "1"
-
- # Enable lpss s0ix
- register "lpss_s0ix_enable" = "1"
-
- # GPE configuration
- # Note that GPE events called out in ASL code rely on this
- # route, i.e., if this route changes then the affected GPE
- # offset bits also need to be changed. This sets the PMC register
- # GPE_CFG fields.
- register "gpe0_dw1" = "PMC_GPE_N_31_0"
- register "gpe0_dw2" = "PMC_GPE_N_63_32"
- register "gpe0_dw3" = "PMC_GPE_SW_31_0"
-
- # Enable I2C0 for audio codec at 400kHz
- register "i2c[0]" = "{
- .speed = I2C_SPEED_FAST,
- .rise_time_ns = 104,
- .fall_time_ns = 52,
- }"
-
- # Enable I2C2 bus early for TPM at 400kHz
- register "i2c[2]" = "{
- .early_init = 1,
- .speed = I2C_SPEED_FAST,
- .rise_time_ns = 57,
- .fall_time_ns = 28,
- }"
-
- # touchscreen at 400kHz
- register "i2c[3]" = "{
- .speed = I2C_SPEED_FAST,
- .rise_time_ns = 76,
- .fall_time_ns = 164,
- }"
-
- # trackpad at 400kHz
- register "i2c[4]" = "{
- .speed = I2C_SPEED_FAST,
- .rise_time_ns = 114,
- .fall_time_ns = 164,
- }"
-
- # digitizer at 400kHz
- register "i2c[5]" = "{
- .speed = I2C_SPEED_FAST,
- .rise_time_ns = 152,
- .fall_time_ns = 30,
- }"
-
- # Minimum SLP S3 assertion width 28ms.
- register "slp_s3_assertion_width_usecs" = "28000"
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
device domain 0 on
- device pci 00.0 on end # - Host Bridge
- device pci 00.1 on end # - DPTF
- device pci 00.2 on end # - NPK
- device pci 02.0 on end # - Gen
- device pci 03.0 on end # - Iunit
- device pci 0d.0 on end # - P2SB
- device pci 0d.1 on end # - PMC
- device pci 0d.2 on end # - SPI
- device pci 0d.3 on end # - Shared SRAM
- device pci 0e.0 on # - Audio
- chip drivers/generic/max98357a
- register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
- register "sdmode_delay" = "5"
- device generic 0 on end
- end
- end
- device pci 11.0 off end # - ISH
- device pci 12.0 off end # - SATA
- device pci 13.0 off end # - Root Port 2 - PCIe-A 0
- device pci 13.1 off end # - Root Port 3 - PCIe-A 1
- device pci 13.2 off end # - Root Port 4 - PCIe-A 2
- device pci 13.3 off end # - Root Port 5 - PCIe-A 3
- device pci 14.0 on
- chip drivers/intel/wifi
- register "wake" = "GPE0_DW3_00"
- device pci 00.0 on end
- end
- end # - Root Port 0 - PCIe-B 0 - Wifi
- device pci 14.1 off end # - Root Port 1 - PCIe-B 1
- device pci 15.0 on end # - XHCI
- device pci 15.1 off end # - XDCI
- device pci 16.0 on # - I2C 0
- chip drivers/i2c/da7219
- register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)"
- register "btn_cfg" = "50"
- register "mic_det_thr" = "500"
- register "jack_ins_deb" = "20"
- register "jack_det_rate" = ""32ms_64ms""
- register "jack_rem_deb" = "1"
- register "a_d_btn_thr" = "0xa"
- register "d_b_btn_thr" = "0x16"
- register "b_c_btn_thr" = "0x21"
- register "c_mic_btn_thr" = "0x3e"
- register "btn_avg" = "4"
- register "adc_1bit_rpt" = "1"
- register "micbias_lvl" = "2600"
- register "mic_amp_in_sel" = ""diff""
- device i2c 1a on end
- end
- end
- device pci 16.1 on end # - I2C 1
- device pci 16.2 on
- chip drivers/i2c/tpm
- register "hid" = ""GOOG0005""
- register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)"
- device i2c 50 on end
- end
- end # - I2C 2
- device pci 16.3 on
- chip drivers/i2c/generic
- register "hid" = ""ELAN0001""
- register "desc" = ""ELAN Touchscreen""
- register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)"
- register "probed" = "1"
- register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
- register "reset_delay_ms" = "20"
- register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
- register "enable_delay_ms" = "1"
- register "has_power_resource" = "1"
- device i2c 10 on end
- end
- end # - I2C 3
- device pci 17.0 on
- chip drivers/i2c/generic
- register "hid" = ""ELAN0000""
- register "desc" = ""ELAN Touchpad""
- register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_18_IRQ)"
- register "wake" = "GPE0_DW1_15"
- register "probed" = "1"
- device i2c 15 on end
- end
- end # - I2C 4
- device pci 17.1 on
- chip drivers/i2c/hid
- register "generic.hid" = ""WCOM50C1""
- register "generic.desc" = ""WCOM Digitizer""
- register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_13_IRQ)"
- register "hid_desc_reg_offset" = "0x1"
- device i2c 0x9 on end
- end
- end # - I2C 5
- device pci 17.2 off end # - I2C 6
- device pci 17.3 off end # - I2C 7
- device pci 18.0 on end # - UART 0
- device pci 18.1 on end # - UART 1
- device pci 18.2 on end # - UART 2
- device pci 18.3 off end # - UART 3
- device pci 19.0 on end # - SPI 0
- device pci 19.1 off end # - SPI 1
- device pci 19.2 off end # - SPI 2
- device pci 1a.0 on end # - PWM
- device pci 1b.0 on end # - SDCARD
- device pci 1c.0 on end # - eMMC
- device pci 1e.0 off end # - SDIO
- device pci 1f.0 on # - LPC
- chip ec/google/chromeec
- device pnp 0c09.0 on end
- end
- end
- device pci 1f.1 on end # - SMBUS
+ device pci 00.0 on end # - Host Bridge
+ device pci 00.1 on end # - DPTF
+ device pci 00.2 on end # - NPK
+ device pci 02.0 on end # - Gen
+ device pci 03.0 on end # - Iunit
+ device pci 0d.0 on end # - P2SB
+ device pci 0d.1 on end # - PMC
+ device pci 0d.2 on end # - SPI
+ device pci 0d.3 on end # - Shared SRAM
+ device pci 0e.0 on end # - Audio
+ device pci 11.0 on end # - ISH
+ device pci 12.0 on end # - SATA
+ device pci 13.0 on end # - PCIe-A 0
+ device pci 13.2 on end # - Onboard Lan
+ device pci 13.3 on end # - PCIe-A 3
+ device pci 14.0 on end # - PCIe-B 0
+ device pci 14.1 on end # - Onboard M2 Slot(Wifi/BT)
+ device pci 15.0 on end # - XHCI
+ device pci 15.1 on end # - XDCI
+ device pci 16.0 on end # - I2C 0
+ device pci 16.1 on end # - I2C 1
+ device pci 16.2 on end # - I2C 2
+ device pci 16.3 on end # - I2C 3
+ device pci 17.0 on end # - I2C 4
+ device pci 17.1 on end # - I2C 5
+ device pci 17.2 on end # - I2C 6
+ device pci 17.3 on end # - I2C 7
+ device pci 18.0 on end # - UART 0
+ device pci 18.1 on end # - UART 1
+ device pci 18.2 on end # - UART 2
+ device pci 18.3 on end # - UART 3
+ device pci 19.0 on end # - SPI 0
+ device pci 19.1 on end # - SPI 1
+ device pci 19.2 on end # - SPI 2
+ device pci 1a.0 on end # - PWM
+ device pci 1b.0 on end # - SDCARD
+ device pci 1c.0 on end # - eMMC
+ device pci 1e.0 on end # - SDIO
+ device pci 1f.0 on end # - LPC
+ device pci 1f.1 on end # - SMBUS
end
end
diff --git a/src/mainboard/intel/leafhill/leafhill.fmd b/src/mainboard/intel/leafhill/leafhill.fmd
deleted file mode 100644
index 3da8467..0000000
--- a/src/mainboard/intel/leafhill/leafhill.fmd
+++ /dev/null
@@ -1,40 +0,0 @@
-FLASH 16M {
- WP_RO at 0x0 0x400000 {
- SI_DESC at 0x0 0x1000
- IFWI at 0x1000 0x1ff000
- RO_VPD at 0x200000 0x4000
- RO_SECTION at 0x204000 0x1fc000 {
- FMAP at 0x0 0x800
- COREBOOT(CBFS)@0x1000 0x1bb000
- RO_UNUSED at 0x1bc000 0x40000
- }
- }
- MISC_RW at 0x400000 0x30000 {
- UNIFIED_MRC_CACHE at 0x0 0x21000 {
- RECOVERY_MRC_CACHE at 0x0 0x10000
- RW_MRC_CACHE at 0x10000 0x10000
- RW_VAR_MRC_CACHE at 0x20000 0x1000
- }
- RW_ELOG at 0x21000 0x3000
- RW_SHARED at 0x24000 0x4000 {
- SHARED_DATA at 0x0 0x2000
- VBLOCK_DEV at 0x2000 0x2000
- }
- RW_VPD at 0x28000 0x2000
- RW_NVRAM at 0x2a000 0x6000
- }
- RW_LEGACY(CBFS)@0xd30000 0x200000
- BIOS_UNUSABLE at 0xf30000 0x4f000
- DEVICE_EXTENSION at 0xf7f000 0x80000
- # Currently, it is required that the BIOS region be a multiple of 8KiB.
- # This is required so that the recovery mechanism can find SIGN_CSE
- # region aligned to 4K at the center of BIOS region. Since the
- # descriptor at the beginning uses 4K and BIOS starts at an offset of
- # 4K, a hole of 4K is created towards the end of the flash to compensate
- # for the size requirement of BIOS region.
- # FIT tool thus creates descriptor with following regions:
- # Descriptor --> 0 to 4K
- # BIOS --> 4K to 0xf7f000
- # Device ext --> 0xf7f000 to 0xfff000
- UNUSED_HOLE at 0xfff000 0x1000
-}
diff --git a/src/mainboard/intel/leafhill/leafhill.fmd.16384 b/src/mainboard/intel/leafhill/leafhill.fmd.16384
new file mode 100644
index 0000000..a91ba9a
--- /dev/null
+++ b/src/mainboard/intel/leafhill/leafhill.fmd.16384
@@ -0,0 +1,14 @@
+FLASH 16M {
+ SI_DESC at 0x0 0x1000
+ IFWI at 0x1000 0x2ff000
+ FMAP at 0x300000 0x800
+ COREBOOT(CBFS)@0x300800 0xc1d800
+ UNIFIED_MRC_CACHE at 0xf1e000 0x21000 {
+ RECOVERY_MRC_CACHE at 0x0 0x10000
+ RW_MRC_CACHE at 0x10000 0x10000
+ RW_VAR_MRC_CACHE at 0x20000 0x1000
+ }
+ BIOS_UNUSABLE at 0xf3f000 0x40000
+ DEVICE_EXTENSION at 0xf7f000 0x7f000
+ UNUSED_HOLE at 0xfff000 0x1000
+}
diff --git a/src/mainboard/intel/leafhill/leafhill.fmd.8192 b/src/mainboard/intel/leafhill/leafhill.fmd.8192
new file mode 100644
index 0000000..3f4d21b
--- /dev/null
+++ b/src/mainboard/intel/leafhill/leafhill.fmd.8192
@@ -0,0 +1,14 @@
+FLASH 8M {
+ SI_DESC at 0x0 0x1000
+ IFWI at 0x1000 0x300000
+ FMAP at 0x321000 0x800
+ COREBOOT(CBFS)@0x321800 0x300000
+ UNIFIED_MRC_CACHE at 0x621800 0x21000 {
+ RECOVERY_MRC_CACHE at 0x0 0x10000
+ RW_MRC_CACHE at 0x10000 0x10000
+ RW_VAR_MRC_CACHE at 0x20000 0x1000
+ }
+ BIOS_UNUSABLE at 0x740000 0x40000
+ DEVICE_EXTENSION at 0x780000 0x7f000
+ UNUSED_HOLE at 0x7ff000 0x1000
+}
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