[coreboot-gerrit] Patch set updated for coreboot: amd/pi/mainboards: Consolidate early duplicated code
Marc Jones (marc@marcjonesconsulting.com)
gerrit at coreboot.org
Sat Feb 25 00:48:58 CET 2017
Marc Jones (marc at marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18434
-gerrit
commit d619b6b2bd1a7cce83bbb3695217d2689f2bfd51
Author: Marshall Dawson <marshalldawson3rd at gmail.com>
Date: Thu Feb 9 09:15:05 2017 -0700
amd/pi/mainboards: Consolidate early duplicated code
Make a common entry function for cache_as_ram_main for use with the
PI-based mainboards. The new function drives the typical setup, BIST
checking, product reporting, and other common functions. This work
takes hints from commit e6af4be.
Add a new car.c file that contains the early steps. This has
weak functions to hook for southbridge and mainboard setup. Some
APUs also get BIST bits masked off.
This patch is intended to prepare for an upcoming change that will
split the CAR setup from the teardown, so that CAR setup may be used
in verstage.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
Original-Reviewed-by: Marc Jones <marcj303 at gmail.com>
(cherry picked from commit 9d1d92826216dee35f80ec40d722a3e8a587e996)
Change-Id: Id10580ecc439df10df26ca99881772f328e7bdd0
Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
src/cpu/amd/pi/00660F01/fixme.c | 7 ++
src/cpu/amd/pi/00670F00/fixme.c | 7 ++
src/cpu/amd/pi/Makefile.inc | 2 +
src/cpu/amd/pi/car.c | 88 +++++++++++++++++++++++
src/cpu/amd/pi/car.h | 30 ++++++++
src/mainboard/amd/bettong/romstage.c | 30 +-------
src/mainboard/amd/db-ft3b-lc/Makefile.inc | 1 +
src/mainboard/amd/db-ft3b-lc/early_mainboard.c | 31 ++++++++
src/mainboard/amd/db-ft3b-lc/romstage.c | 39 +---------
src/mainboard/amd/gardenia/romstage.c | 29 +-------
src/mainboard/amd/lamar/Makefile.inc | 2 +
src/mainboard/amd/lamar/early_mainboard.c | 44 ++++++++++++
src/mainboard/amd/lamar/romstage.c | 48 +------------
src/mainboard/amd/olivehillplus/Makefile.inc | 1 +
src/mainboard/amd/olivehillplus/early_mainboard.c | 44 ++++++++++++
src/mainboard/amd/olivehillplus/romstage.c | 47 +-----------
src/mainboard/bap/ode_e21XX/Makefile.inc | 1 +
src/mainboard/bap/ode_e21XX/early_mainboard.c | 37 ++++++++++
src/mainboard/bap/ode_e21XX/romstage.c | 43 +----------
src/mainboard/pcengines/apu2/Makefile.inc | 1 +
src/mainboard/pcengines/apu2/early_mainboard.c | 67 +++++++++++++++++
src/mainboard/pcengines/apu2/romstage.c | 74 +------------------
src/southbridge/amd/pi/hudson/early_setup.c | 11 +++
23 files changed, 388 insertions(+), 296 deletions(-)
diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c
index f244b98..fb1dfd7 100644
--- a/src/cpu/amd/pi/00660F01/fixme.c
+++ b/src/cpu/amd/pi/00660F01/fixme.c
@@ -16,6 +16,7 @@
#include <cpu/x86/mtrr.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include "amdlib.h"
+#include <cpu/amd/pi/car.h>
void amd_initcpuio(void)
{
@@ -91,3 +92,9 @@ void amd_initmmio(void)
LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
#endif
}
+
+unsigned long car_bist_mask_bist(unsigned long bist)
+{
+ /* Mask bit 31. One result of Silicon Observation */
+ return bist & 0x7FFFFFFF;
+}
diff --git a/src/cpu/amd/pi/00670F00/fixme.c b/src/cpu/amd/pi/00670F00/fixme.c
index 272552d..3f02d7a 100644
--- a/src/cpu/amd/pi/00670F00/fixme.c
+++ b/src/cpu/amd/pi/00670F00/fixme.c
@@ -16,6 +16,7 @@
#include <cpu/x86/mtrr.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include "amdlib.h"
+#include <cpu/amd/pi/car.h>
void amd_initcpuio(void)
{
@@ -95,3 +96,9 @@ void amd_initmmio(void)
LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
#endif
}
+
+unsigned long car_bist_mask_bist(unsigned long bist)
+{
+ /* Mask bit 31. One result of Silicon Observation */
+ return bist & 0x7FFFFFFF;
+}
diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc
index 0e31d9f..ce60833 100644
--- a/src/cpu/amd/pi/Makefile.inc
+++ b/src/cpu/amd/pi/Makefile.inc
@@ -18,6 +18,8 @@ subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
subdirs-$(CONFIG_CPU_AMD_PI_00670F00) += 00670F00
subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01
+romstage-y += car.c
+
romstage-y += s3_resume.c
ramstage-y += s3_resume.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c
diff --git a/src/cpu/amd/pi/car.c b/src/cpu/amd/pi/car.c
new file mode 100644
index 0000000..62c5338
--- /dev/null
+++ b/src/cpu/amd/pi/car.c
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/early_variables.h>
+#include <console/console.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/bist.h>
+#include <cpu/amd/car.h>
+#include <cpu/amd/pi/car.h>
+#include <northbridge/amd/pi/agesawrapper.h>
+#include <timestamp.h>
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ u32 val;
+
+#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
+ /* Initialize timestamp book keeping only once. */
+ timestamp_init(timestamp_get());
+#endif
+
+ post_code(0x30);
+
+ /* Must come first to enable PCI MMCONF. */
+ amd_initmmio();
+
+ if (!cpu_init_detectedx && boot_cpu()){
+ /* Call into pre-console init code then initialize console. */
+ post_code(0x31);
+ car_sb_pre_console_init();
+
+ post_code(0x32);
+ car_mainboard_pre_console_init();
+
+ post_code(0x33);
+ console_init();
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(car_bist_mask_bist(bist));
+
+ /* Load MPB */
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+
+ post_code(0x35);
+ car_sb_post_console_init();
+ post_code(0x36);
+ car_mainboard_post_console_init();
+
+ cache_as_ram_stage_main();
+}
+
+unsigned long __attribute__((weak)) car_bist_mask_bist(unsigned long bist)
+{
+ return bist;
+}
+
+void __attribute__((weak)) car_mainboard_pre_console_init(void)
+{
+}
+
+void __attribute__((weak)) car_sb_pre_console_init(void)
+{
+}
+
+void __attribute__((weak)) car_mainboard_post_console_init(void)
+{
+}
+
+void __attribute__((weak)) car_sb_post_console_init(void)
+{
+}
diff --git a/src/cpu/amd/pi/car.h b/src/cpu/amd/pi/car.h
new file mode 100644
index 0000000..98da75d
--- /dev/null
+++ b/src/cpu/amd/pi/car.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef PI_SPLIT_CAR_H
+#define PI_SPLIT_CAR_H
+
+/* Early initialization immediately after CAR setup */
+void cache_as_ram_stage_main(void);
+
+unsigned long car_bist_mask_bist(unsigned long bist);
+void car_mainboard_pre_console_init(void);
+void car_sb_pre_console_init(void);
+
+void car_mainboard_post_console_init(void);
+void car_sb_post_console_init(void);
+
+#endif
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c
index 6b12afc..c881337 100644
--- a/src/mainboard/amd/bettong/romstage.c
+++ b/src/mainboard/amd/bettong/romstage.c
@@ -17,45 +17,19 @@
#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/stages.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/bist.h>
#include <cpu/amd/car.h>
+#include <cpu/amd/pi/car.h>
#include <cpu/amd/pi/s3_resume.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <southbridge/amd/pi/hudson/hudson.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_stage_main(void)
{
- u32 val;
#if CONFIG_HAVE_ACPI_RESUME
void *resume_backup_memory;
#endif
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- hudson_lpc_port80();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
-
-#if IS_ENABLED(CONFIG_HUDSON_UART)
- configure_hudson_uart();
-#endif
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
post_code(0x38);
diff --git a/src/mainboard/amd/db-ft3b-lc/Makefile.inc b/src/mainboard/amd/db-ft3b-lc/Makefile.inc
index 97c761f..01d99ac 100644
--- a/src/mainboard/amd/db-ft3b-lc/Makefile.inc
+++ b/src/mainboard/amd/db-ft3b-lc/Makefile.inc
@@ -15,6 +15,7 @@
romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c
+romstage-y += early_mainboard.c
ramstage-y += BiosCallOuts.c
ramstage-y += OemCustomize.c
diff --git a/src/mainboard/amd/db-ft3b-lc/early_mainboard.c b/src/mainboard/amd/db-ft3b-lc/early_mainboard.c
new file mode 100644
index 0000000..7d471eb
--- /dev/null
+++ b/src/mainboard/amd/db-ft3b-lc/early_mainboard.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cpu/amd/pi/car.h>
+
+void car_mainboard_pre_console_init(void)
+{
+ /*
+ * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+ * LpcClk[1:0]". This following register setting has been
+ * replicated in every reference design since Parmer, so it is
+ * believed to be required even though it is not documented in
+ * the SoC BKDGs. Without this setting, there is no serial
+ * output.
+ */
+ outb(0xD2, 0xcd6);
+ outb(0x00, 0xcd7);
+}
diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c
index 79cc0f9..e67f1fb 100644
--- a/src/mainboard/amd/db-ft3b-lc/romstage.c
+++ b/src/mainboard/amd/db-ft3b-lc/romstage.c
@@ -26,49 +26,14 @@
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
+#include <cpu/amd/pi/car.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>
#include <cpu/amd/pi/s3_resume.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_stage_main(void)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- /*
- * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
- * LpcClk[1:0]". This following register setting has been
- * replicated in every reference design since Parmer, so it is
- * believed to be required even though it is not documented in
- * the SoC BKDGs. Without this setting, there is no serial
- * output.
- */
- outb(0xD2, 0xcd6);
- outb(0x00, 0xcd7);
-
- hudson_lpc_port80();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
-
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c
index eca9d3b..1d2d05b 100644
--- a/src/mainboard/amd/gardenia/romstage.c
+++ b/src/mainboard/amd/gardenia/romstage.c
@@ -17,44 +17,19 @@
#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/stages.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/bist.h>
#include <cpu/amd/car.h>
+#include <cpu/amd/pi/car.h>
#include <cpu/amd/pi/s3_resume.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <southbridge/amd/pi/hudson/hudson.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_stage_main(void)
{
- u32 val;
#if CONFIG_HAVE_ACPI_RESUME
void *resume_backup_memory;
#endif
- amd_initmmio();
- hudson_lpc_port80();
- hudson_lpc_decode();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
-
-#if IS_ENABLED(CONFIG_HUDSON_UART)
- configure_hudson_uart();
-#endif
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
post_code(0x38);
diff --git a/src/mainboard/amd/lamar/Makefile.inc b/src/mainboard/amd/lamar/Makefile.inc
index 37c1dce..794c6dc 100644
--- a/src/mainboard/amd/lamar/Makefile.inc
+++ b/src/mainboard/amd/lamar/Makefile.inc
@@ -13,6 +13,8 @@
# GNU General Public License for more details.
#
+romstage-y += early_mainboard.c
+
romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c
diff --git a/src/mainboard/amd/lamar/early_mainboard.c b/src/mainboard/amd/lamar/early_mainboard.c
new file mode 100644
index 0000000..65aace1
--- /dev/null
+++ b/src/mainboard/amd/lamar/early_mainboard.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 - 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cpu/amd/pi/car.h>
+#include <southbridge/amd/common/amd_defs.h>
+#include <southbridge/amd/pi/hudson/hudson.h>
+#include "superio/fintek/f81216h/f81216h.h"
+
+#define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1)
+
+
+void car_mainboard_pre_console_init(void)
+{
+ /*
+ * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+ * LpcClk[1:0]". This following register setting has been
+ * replicated in every reference design since Parmer, so it is
+ * believed to be required even though it is not documented in
+ * the SoC BKDGs. Without this setting, there is no serial
+ * output.
+ */
+ outb(0xD2, 0xcd6);
+ outb(0x00, 0xcd7);
+
+ outb(0x24, 0xCD6);
+ outb(0x01, 0xCD7);
+ *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */
+ *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */
+
+ f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777);
+}
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index bda8c0f..9204e90 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -21,11 +21,11 @@
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp_def.h>
-#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
+#include <cpu/amd/pi/car.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <cpu/x86/bist.h>
@@ -34,53 +34,9 @@
#include <southbridge/amd/pi/hudson/hudson.h>
#include <cpu/amd/pi/s3_resume.h>
#include "cbmem.h"
-#include "superio/fintek/f81216h/f81216h.h"
-#define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1)
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_stage_main(void)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- /*
- * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
- * LpcClk[1:0]". This following register setting has been
- * replicated in every reference design since Parmer, so it is
- * believed to be required even though it is not documented in
- * the SoC BKDGs. Without this setting, there is no serial
- * output.
- */
- outb(0xD2, 0xcd6);
- outb(0x00, 0xcd7);
-
- hudson_lpc_decode();
-
- outb(0x24, 0xCD6);
- outb(0x01, 0xCD7);
- *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */
- *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */
-
- hudson_lpc_port80();
-
- if (!cpu_init_detectedx) {
- post_code(0x30);
- f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777);
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
post_code(0x38);
diff --git a/src/mainboard/amd/olivehillplus/Makefile.inc b/src/mainboard/amd/olivehillplus/Makefile.inc
index 37c1dce..c1ac631 100644
--- a/src/mainboard/amd/olivehillplus/Makefile.inc
+++ b/src/mainboard/amd/olivehillplus/Makefile.inc
@@ -15,6 +15,7 @@
romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c
+romstage-y += early_mainboard.c
ramstage-y += BiosCallOuts.c
ramstage-y += OemCustomize.c
diff --git a/src/mainboard/amd/olivehillplus/early_mainboard.c b/src/mainboard/amd/olivehillplus/early_mainboard.c
new file mode 100644
index 0000000..d394c9a
--- /dev/null
+++ b/src/mainboard/amd/olivehillplus/early_mainboard.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 - 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cpu/amd/pi/car.h>
+
+void car_mainboard_pre_console_init(void)
+{
+ /*
+ * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+ * LpcClk[1:0]". This following register setting has been
+ * replicated in every reference design since Parmer, so it is
+ * believed to be required even though it is not documented in
+ * the SoC BKDGs. Without this setting, there is no serial
+ * output.
+ */
+ outb(0xD2, 0xcd6);
+ outb(0x00, 0xcd7);
+}
+
+void car_mainboard_post_console_init(void)
+{
+ /*
+ * This refers to LpcClkDrvSth settling time. Without this setting, processor
+ * initialization is slow or incorrect, so this wait has been replicated from
+ * earlier development boards.
+ */
+ {
+ int i;
+ for(i = 0; i < 200000; i++) inb(0xCD6);
+ }
+}
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 534a8e5..02fa3d1 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -26,6 +26,7 @@
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
+#include <cpu/amd/pi/car.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <cpu/x86/bist.h>
@@ -33,52 +34,8 @@
#include <southbridge/amd/pi/hudson/hudson.h>
#include <cpu/amd/pi/s3_resume.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_stage_main(void)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- /*
- * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
- * LpcClk[1:0]". This following register setting has been
- * replicated in every reference design since Parmer, so it is
- * believed to be required even though it is not documented in
- * the SoC BKDGs. Without this setting, there is no serial
- * output.
- */
- outb(0xD2, 0xcd6);
- outb(0x00, 0xcd7);
-
- hudson_lpc_port80();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
-
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- /*
- * This refers to LpcClkDrvSth settling time. Without this setting, processor
- * initialization is slow or incorrect, so this wait has been replicated from
- * earlier development boards.
- */
- {
- int i;
- for(i = 0; i < 200000; i++) inb(0xCD6);
- }
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/bap/ode_e21XX/Makefile.inc b/src/mainboard/bap/ode_e21XX/Makefile.inc
index b0ce627..f6a27ad 100644
--- a/src/mainboard/bap/ode_e21XX/Makefile.inc
+++ b/src/mainboard/bap/ode_e21XX/Makefile.inc
@@ -15,6 +15,7 @@
romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c
+romstage-y += early_mainboard.c
ramstage-y += BiosCallOuts.c
ramstage-y += OemCustomize.c
diff --git a/src/mainboard/bap/ode_e21XX/early_mainboard.c b/src/mainboard/bap/ode_e21XX/early_mainboard.c
new file mode 100644
index 0000000..b7ffbbb
--- /dev/null
+++ b/src/mainboard/bap/ode_e21XX/early_mainboard.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cpu/amd/pi/car.h>
+#include <superio/fintek/common/fintek.h>
+#include <superio/fintek/f81866d/f81866d.h>
+
+#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1)
+
+void car_mainboard_pre_console_init(void)
+{
+ /*
+ * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+ * LpcClk[1:0]". This following register setting has been
+ * replicated in every reference design since Parmer, so it is
+ * believed to be required even though it is not documented in
+ * the SoC BKDGs. Without this setting, there is no serial
+ * output.
+ */
+ outb(0xD2, 0xcd6);
+ outb(0x00, 0xcd7);
+
+ fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c
index 5deeaa8..b82b13f 100644
--- a/src/mainboard/bap/ode_e21XX/romstage.c
+++ b/src/mainboard/bap/ode_e21XX/romstage.c
@@ -26,53 +26,14 @@
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
+#include <cpu/amd/pi/car.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>
#include <cpu/amd/pi/s3_resume.h>
-#include <superio/fintek/common/fintek.h>
-#include <superio/fintek/f81866d/f81866d.h>
-
-#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_stage_main(void)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- /*
- * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
- * LpcClk[1:0]". This following register setting has been
- * replicated in every reference design since Parmer, so it is
- * believed to be required even though it is not documented in
- * the SoC BKDGs. Without this setting, there is no serial
- * output.
- */
- outb(0xD2, 0xcd6);
- outb(0x00, 0xcd7);
-
- hudson_lpc_port80();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
- fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE);
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc
index 77c6d78..2936f36 100644
--- a/src/mainboard/pcengines/apu2/Makefile.inc
+++ b/src/mainboard/pcengines/apu2/Makefile.inc
@@ -16,6 +16,7 @@
romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c
romstage-y += gpio_ftns.c
+romstage-y += early_mainboard.c
ramstage-y += BiosCallOuts.c
ramstage-y += OemCustomize.c
diff --git a/src/mainboard/pcengines/apu2/early_mainboard.c b/src/mainboard/pcengines/apu2/early_mainboard.c
new file mode 100644
index 0000000..9bd4ba3
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/early_mainboard.c
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 - 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cpu/amd/pi/car.h>
+#include <southbridge/amd/pi/hudson/hudson.h>
+#include <northbridge/amd/pi/agesawrapper_call.h>
+#include <Fch/Fch.h>
+#include "gpio_ftns.h"
+
+static void early_lpc_init(void)
+{
+ u32 setting = 0x0;
+
+ //
+ // Configure output disabled, value low, pull up/down disabled
+ //
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_32, Function0, GPIO_32, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_49, Function2, GPIO_49, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_50, Function2, GPIO_50, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_71, Function0, GPIO_71, setting);
+ //
+ // Configure output enabled, value low, pull up/down disabled
+ //
+ setting = 0x1 << GPIO_OUTPUT_ENABLE;
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_57, Function1, GPIO_57, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_58, Function1, GPIO_58, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_59, Function3, GPIO_59, setting);
+ //
+ // Configure output enabled, value high, pull up/down disabled
+ //
+ setting = 0x1 << GPIO_OUTPUT_ENABLE | 0x1 << GPIO_OUTPUT_VALUE;
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_51, Function2, GPIO_51, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_55, Function3, GPIO_55, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_64, Function2, GPIO_64, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_68, Function0, GPIO_68, setting);
+}
+
+void car_mainboard_pre_console_init(void)
+{
+ /*
+ * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+ * LpcClk[1:0]". This following register setting has been
+ * replicated in every reference design since Parmer, so it is
+ * believed to be required even though it is not documented in
+ * the SoC BKDGs. Without this setting, there is no serial
+ * output.
+ */
+ outb(0xD2, 0xcd6);
+ outb(0x00, 0xcd7);
+
+ early_lpc_init();
+
+ hudson_clk_output_48Mhz();
+}
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index f8ed63c..9dbf06c 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -26,54 +26,13 @@
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
+#include <cpu/amd/pi/car.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
#include <cpu/amd/pi/s3_resume.h>
-#include <Fch/Fch.h>
-#include "gpio_ftns.h"
-
-static void early_lpc_init(void);
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_stage_main(void)
{
- u32 val;
-
- /*
- * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
- * LpcClk[1:0]". This following register setting has been
- * replicated in every reference design since Parmer, so it is
- * believed to be required even though it is not documented in
- * the SoC BKDGs. Without this setting, there is no serial
- * output.
- */
- outb(0xD2, 0xcd6);
- outb(0x00, 0xcd7);
-
- amd_initmmio();
-
- hudson_lpc_port80();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
- early_lpc_init();
-
- hudson_clk_output_48Mhz();
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
@@ -114,32 +73,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x54); /* Should never see this post code. */
}
-
-
-static void early_lpc_init(void)
-{
- u32 setting = 0x0;
-
- //
- // Configure output disabled, value low, pull up/down disabled
- //
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_32, Function0, GPIO_32, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_49, Function2, GPIO_49, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_50, Function2, GPIO_50, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_71, Function0, GPIO_71, setting);
- //
- // Configure output enabled, value low, pull up/down disabled
- //
- setting = 0x1 << GPIO_OUTPUT_ENABLE;
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_57, Function1, GPIO_57, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_58, Function1, GPIO_58, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_59, Function3, GPIO_59, setting);
- //
- // Configure output enabled, value high, pull up/down disabled
- //
- setting = 0x1 << GPIO_OUTPUT_ENABLE | 0x1 << GPIO_OUTPUT_VALUE;
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_51, Function2, GPIO_51, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_55, Function3, GPIO_55, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_64, Function2, GPIO_64, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_68, Function0, GPIO_68, setting);
-}
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index 0ac2316..fa68624 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -26,6 +26,7 @@
#include "hudson.h"
#include "pci_devs.h"
#include <Fch/Fch.h>
+#include <cpu/amd/pi/car.h>
#if IS_ENABLED(CONFIG_HUDSON_UART)
@@ -53,6 +54,16 @@ void configure_hudson_uart(void)
#endif
+void car_sb_pre_console_init(void)
+{
+ hudson_lpc_port80();
+ hudson_lpc_decode();
+
+#if IS_ENABLED(CONFIG_HUDSON_UART)
+ configure_hudson_uart();
+#endif
+}
+
void hudson_pci_port80(void)
{
u8 byte;
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