[coreboot-gerrit] Patch set updated for coreboot: google/gru: Tuning USB 2.0 PHY0 and PHY1 squelch detection threshold

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18462

-gerrit

commit 069e83c3e9fc268024b5bca78d017bbf4feb91e9
Author: William wu <wulf at rock-chips.com>
Date:   Mon Jan 23 20:54:22 2017 +0800

    google/gru: Tuning USB 2.0 PHY0 and PHY1 squelch detection threshold
    
    According to USB 2.0 Spec Table 7-7, the High-speed squelch
    detection threshold Min 100mV and Max 150mV, and we set USB
    2.0 PHY0 and PHY1 squelch detection threshold to 150mV by
    default, so if the amplitude of differential voltage envelope
    is < 150 mV, the USB 2.0 PHYs envelope detector will indicate
    it as squelch.
    
    On Kevin board, if we connect usb device with Samsung U2 cable,
    we can see that the impedance of U2 cable is too big according
    to the eye-diagram test report, and this cause serious signal
    attenuation at the end of receiver, the amplitude of differential
    voltage falls below 150mV.
    
    This patch aims to reduce the PHY0 and PHY1 otg-ports squelch
    detection threshold to 125mV (host-ports still use 150mV by
    default), this is helpful to increase USB 2.0 PHY compatibility.
    
    BRANCH=gru
    BUG=chrome-os-partner:62320
    TEST=Plug Samsung U2 cable + SEC P3 HDD 500GB/Galaxy S3 into
    Type-C port, check if the USB device can be detected.
    
    Change-Id: Ia0a2d354781c2ac757938409490f7c4eecdffe61
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 7d74311c25762668386061234df0562f84b7203e
    Original-Change-Id: Ib20772f8fc2484d34c69f5938818aaa81ded7ed8
    Original-Signed-off-by: William wu <wulf at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/431015
    Original-Commit-Ready: Caesar Wang <wxt at rock-chips.com>
    Original-Tested-by: Inno Park <ih.yoo.park at samsung.com>
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
 src/mainboard/google/gru/mainboard.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c
index 5926e49..bb9b6fc 100644
--- a/src/mainboard/google/gru/mainboard.c
+++ b/src/mainboard/google/gru/mainboard.c
@@ -260,15 +260,20 @@ static void setup_usb(void)
 		RK_CLRSETBITS(0xffff, 0xa7));
 
 	/*
-	 * Disable the pre-emphasize in eop state and chirp
+	 * 1. Disable the pre-emphasize in eop state and chirp
 	 * state to avoid mis-trigger the disconnect detection
 	 * and also avoid high-speed handshake fail for PHY0
 	 * and PHY1 consist of otg-port and host-port.
+	 *
+	 * 2. Configure PHY0 and PHY1 otg-ports squelch detection
+	 * threshold to 125mV (default is 150mV).
 	 */
-	write32(&rk3399_grf->usbphy0_ctrl[0], RK_CLRBITS(0x3));
-	write32(&rk3399_grf->usbphy1_ctrl[0], RK_CLRBITS(0x3));
-	write32(&rk3399_grf->usbphy0_ctrl[13], RK_CLRBITS(0x3));
-	write32(&rk3399_grf->usbphy1_ctrl[13], RK_CLRBITS(0x3));
+	write32(&rk3399_grf->usbphy0_ctrl[0],
+		RK_CLRSETBITS(7 << 13 | 3 << 0, 6 << 13));
+	write32(&rk3399_grf->usbphy1_ctrl[0],
+		RK_CLRSETBITS(7 << 13 | 3 << 0, 6 << 13));
+	write32(&rk3399_grf->usbphy0_ctrl[13], RK_CLRBITS(3 << 0));
+	write32(&rk3399_grf->usbphy1_ctrl[13], RK_CLRBITS(3 << 0));
 
 	/*
 	 * ODT auto compensation bypass, and set max driver