[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: Use intel/common/block/systemagent code

[Subrata Banik (subrata.banik@intel.com)]

Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18456

-gerrit

commit fe6300ca1d17d4772b297fdd00a147fc418708e8
Author: Barnali Sarkar <barnali.sarkar at intel.com>
Date:   Wed Feb 22 18:43:43 2017 +0530

    soc/intel/skylake: Use intel/common/block/systemagent code
    
    Change-Id: Ib471ef3d3ae96b69e2bdfaf81554325d0393900d
    Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
---
 src/soc/intel/skylake/Kconfig                 |  1 +
 src/soc/intel/skylake/Makefile.inc            |  1 -
 src/soc/intel/skylake/bootblock/systemagent.c | 43 ---------------------------
 3 files changed, 1 insertion(+), 44 deletions(-)

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 132fa6d..90f87ab 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -52,6 +52,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_LPSS_I2C
 	select SOC_INTEL_COMMON_NHLT
 	select SOC_INTEL_COMMON_RESET
+	select SOC_INTEL_COMMON_SA
 	select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
 	select SOC_INTEL_COMMON_XHCI
 	select SMM_TSEG
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 181e17b..dfda301 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -15,7 +15,6 @@ bootblock-y += bootblock/i2c.c
 bootblock-y += bootblock/pch.c
 bootblock-y += bootblock/report_platform.c
 bootblock-y += bootblock/smbus.c
-bootblock-y += bootblock/systemagent.c
 bootblock-y += flash_controller.c
 bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c
 bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c
diff --git a/src/soc/intel/skylake/bootblock/systemagent.c b/src/soc/intel/skylake/bootblock/systemagent.c
deleted file mode 100644
index e76d4d2..0000000
--- a/src/soc/intel/skylake/bootblock/systemagent.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- * Copyright (C) 2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <soc/bootblock.h>
-#include <soc/pci_devs.h>
-#include <soc/systemagent.h>
-
-void bootblock_systemagent_early_init(void)
-{
-	uint32_t reg;
-
-	/*
-	 * The "io" variant of the config access is explicitly used to
-	 * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
-	 * to true. That way all subsequent non-explicit config accesses use
-	 * MCFG. This code also assumes that bootblock_northbridge_init() is
-	 * the first thing called in the non-asm boot block code. The final
-	 * assumption is that no assembly code is using the
-	 * CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
-	 *
-	 * The PCIEXBAR is assumed to live in the memory mapped IO space under
-	 * 4GiB.
-	 */
-	reg = 0;
-	pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
-	reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
-	pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg);
-}