[coreboot-gerrit] Patch set updated for coreboot: soc/intel/common/block: [WIP]Add Intel common systemagent support

[Subrata Banik (subrata.banik@intel.com)]

Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18454

-gerrit

commit f6dc1ce49833cdce2dd7d96c44100070bfd70bd9
Author: Barnali Sarkar <barnali.sarkar at intel.com>
Date:   Wed Feb 15 20:09:10 2017 +0530

    soc/intel/common/block: [WIP]Add Intel common systemagent support
    
    Create common Intel systemagent code.
    This code currently contains the SA initialization
    required in Bootblock phase, which has the following programming-
    * Set PCIEXBAR
    * Clear TSEG register
    More code will get added up in the subsequent phases.
    
    Change-Id: Ib8a77aec8b20bafd4175048d442701250f1aa9c8
    Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
---
 .../common/block/include/intelblocks/pci_devs.h    | 37 +++++++++++++++++
 .../common/block/include/intelblocks/systemagent.h | 31 ++++++++++++++
 src/soc/intel/common/block/systemagent/Kconfig     |  4 ++
 .../intel/common/block/systemagent/Makefile.inc    |  5 +++
 .../intel/common/block/systemagent/systemagent.c   | 48 ++++++++++++++++++++++
 5 files changed, 125 insertions(+)

diff --git a/src/soc/intel/common/block/include/intelblocks/pci_devs.h b/src/soc/intel/common/block/include/intelblocks/pci_devs.h
new file mode 100644
index 0000000..d42e930
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/pci_devs.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_PCI_DEVS_H_
+#define _SOC_PCI_DEVS_H_
+
+#include <device/pci_def.h>
+#include <rules.h>
+
+#define _SA_DEVFN(slot)		PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
+#define _PCH_DEVFN(slot, func)	PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
+
+#if ENV_RAMSTAGE
+#include <device/device.h>
+#include <device/pci_def.h>
+#define _SA_DEV(slot)		dev_find_slot(0, _SA_DEVFN(slot))
+#define _PCH_DEV(slot, func)	dev_find_slot(0, _PCH_DEVFN(slot, func))
+#else
+#include <arch/io.h>
+#define _SA_DEV(slot)		PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
+#define _PCH_DEV(slot, func)	PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
+#endif
+
+#endif
+
diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h
new file mode 100644
index 0000000..16ef426
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_SYSTEM_AGENT_H_
+#define _SOC_SYSTEM_AGENT_H_
+
+/* System Agent Devices */
+#define SA_DEV_SLOT_ROOT	0x00
+#define  SA_DEVFN_ROOT		_SA_DEVFN(ROOT)
+#define  SA_DEV_ROOT		_SA_DEV(ROOT)
+
+/* PCI Config Registers */
+#define PCIEXBAR	0x60
+#define TSEG		0xb8	/* TSEG base */
+
+void bootblock_systemagent_early_init(void);
+
+#endif
+
diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig
new file mode 100644
index 0000000..b060bd1
--- /dev/null
+++ b/src/soc/intel/common/block/systemagent/Kconfig
@@ -0,0 +1,4 @@
+config SOC_INTEL_COMMON_SA
+	bool
+	help
+	  Intel Processor common System Agent support
diff --git a/src/soc/intel/common/block/systemagent/Makefile.inc b/src/soc/intel/common/block/systemagent/Makefile.inc
new file mode 100644
index 0000000..9544767
--- /dev/null
+++ b/src/soc/intel/common/block/systemagent/Makefile.inc
@@ -0,0 +1,5 @@
+ifeq ($(CONFIG_SOC_INTEL_COMMON_SA),y)
+
+bootblock-y += systemagent.c
+
+endif
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
new file mode 100644
index 0000000..1c59d1f
--- /dev/null
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <intelblocks/systemagent.h>
+#include <intelblocks/pci_devs.h>
+
+void bootblock_systemagent_early_init(void)
+{
+	uint32_t reg;
+
+	/*
+	 * The "io" variant of the config access is explicitly used to
+	 * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
+	 * to true. That way all subsequent non-explicit config accesses use
+	 * MCFG. This code also assumes that bootblock_northbridge_init() is
+	 * the first thing called in the non-asm boot block code. The final
+	 * assumption is that no assembly code is using the
+	 * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses.
+	 *
+	 * The PCIEXBAR is assumed to live in the memory mapped IO space under
+	 * 4GiB.
+	 */
+	reg = 0;
+	pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
+	reg = CONFIG_MMCONF_BASE_ADDRESS | 1; /* 64MiB - 0-63 buses. */
+	pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg);
+
+	/*
+	 * Clear TSEG register - TSEG register comes out of reset with a
+	 * non-zero default value. Clear this register to ensure that there are
+	 * no surprises in CBMEM handling.
+	 */
+	pci_io_write_config32(SA_DEV_ROOT, TSEG, 0);
+}
+