[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: Use intel/common/basecode/bootblock stage

[Subrata Banik (subrata.banik@intel.com)]

Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18459

-gerrit

commit ed1694e48df159f6e46b3ef5b5a4c25b8325cda5
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Wed Feb 22 19:30:21 2017 +0530

    soc/intel/skylake: Use intel/common/basecode/bootblock stage
    
    TEST=Booted till post code 0x2b and ensure its execute
    PCIEXBAR programming bootblock_systemagent_early_init()
    
    Change-Id: I120aceb55e58fb11f97dcc3bd04bf5cfdc8c3826
    Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
 src/soc/intel/skylake/Kconfig               |  1 +
 src/soc/intel/skylake/Makefile.inc          |  1 -
 src/soc/intel/skylake/bootblock/bootblock.c | 51 -----------------------------
 3 files changed, 1 insertion(+), 52 deletions(-)

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 90f87ab..cc26b3f 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS
 	select RELOCATABLE_MODULES
 	select RELOCATABLE_RAMSTAGE
 	select RTC
+	select SOC_INTEL_BASECODE
 	select SOC_INTEL_CAR_BIG_CORE
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index dfda301..425ef41 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -9,7 +9,6 @@ subdirs-y += ../../../cpu/x86/mtrr
 subdirs-y += ../../../cpu/x86/smm
 subdirs-y += ../../../cpu/x86/tsc
 
-bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/cpu.c
 bootblock-y += bootblock/i2c.c
 bootblock-y += bootblock/pch.c
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
deleted file mode 100644
index 93a031f..0000000
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Intel Corporation..
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <bootblock_common.h>
-#include <soc/bootblock.h>
-
-void asmlinkage bootblock_c_entry(uint64_t base_timestamp)
-{
-	/* Call lib/bootblock.c main */
-	bootblock_main_with_timestamp(base_timestamp);
-}
-
-void bootblock_soc_early_init(void)
-{
-	bootblock_systemagent_early_init();
-	bootblock_pch_early_init();
-	bootblock_cpu_init();
-	pch_early_iorange_init();
-
-	if (IS_ENABLED(CONFIG_UART_DEBUG))
-		pch_uart_init();
-}
-
-void bootblock_soc_init(void)
-{
-	/* FSP 2.0 does not provide FSP-T/TempRamInit init support yet */
-	if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1))
-		bootblock_fsp_temp_ram_init();
-
-	/*
-	 * Perform early chipset initialization before fsp memory init
-	 * example: pirq->irq programming, enabling smbus, set pmcbase
-	 * and abase, i2c programming and print platform info
-	 */
-	report_platform_info();
-	set_max_freq();
-	pch_early_init();
-	i2c_early_init();
-}